ZHCSCR3C October   2012  – August 2014 DS125BR111

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics — Serial Management Bus Interface
    7. 7.7 Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Datapath Blocks
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Control Mode
      2. 8.4.2 SMBus Mode
      3. 8.4.3 Signal Conditioning Settings
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 Transfer Of Data Via The SMBus
      2. 8.6.2 SMBus Transactions
      3. 8.6.3 Writing a Register
      4. 8.6.4 Reading a Register
      5. 8.6.5 SMBus Register Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Signal Integrity
      2. 9.1.2 RX-Detect in SAS/SATA Applications
      3. 9.1.3 PCIe Applications
        1. 9.1.3.1 RXDET When Using SMBus Modes
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13机械封装和可订购信息

9 Application and Implementation

9.1 Application Information

9.1.1 Signal Integrity

In SAS and PCIe applications, specifications require Rx-Tx link training to establish and optimize signal conditioning settings for data rates up to 12 Gbps. In link training, the Rx partner requests a series of FIR coefficients from the TX partner at speed. This polling sequence is designed to pre-condition the signal path with an optimized link between the endpoints. Link training occurs at the following data-rates:

Table 10. Link Training Data-Rates

PROTOCOL MAXIMUM DATA-RATE (Gbps) ALTERNATIVE DATA RATES (Gbps)
SAS 12.0 6.0, 3.0
PCIe 8.0 5.0, 2.5

The DS125BR111 works to extend the reach possible by using active linear equalization to the channel, boosting attenuated signals so that they can be more easily recovered at the Rx. The repeater outputs are specially designed to be transparent to TX FIR signaling in order to pass information critical for optimal link training to the Rx. Suggested settings for the A-channels and B-channels in a SAS or PCIe environment are given in the table below. Further adjustments to EQ and VOD settings may optimize signal margin on the link for different system applications:

Table 11. Pin Mode Device Settings

CHANNEL SETTINGS PIN MODE
EQx Level 4
VOD_SEL Level 7 (1)
VODx_DB 0 dB (0)

Table 12. SMBus Mode Device Settings

CHANNEL SETTINGS SMBus REGISTER VALUE
EQ 0x03
VOD 110'b or 111'b
VODx_DB 000'b

9.1.2 RX-Detect in SAS/SATA Applications

Unlike PCIe systems, SAS/SATA systems use a low speed Out-Of-Band or OOB communications sequence to detect and communicate between SAS Controllers/Expanders and target drives. This communication eliminates the need to detect for endpoints like PCIe. For SAS systems, it is recommended to tie the RXDET pin high. This will ensure any OOB sequences sent from the Controller/Expander will reach the target drive without any additional latency due to the termination detection sequence defined by PCIe.

9.1.3 PCIe Applications

9.1.3.1 RXDET When Using SMBus Modes

PCIe systems use an input termination polling and detection sequence to begin the PCIe bus configuration process. When using PIN MODE configuration the RXDET pin should be left Floating to allow for this process to begin upon power-up of the DS125BR111 device. If SMBus Slave MODE configuration is required, the SMBus register write sequence in Table 13 should be initiated upon power-up of the DS125BR111.

  • Pin Settings for DS125BR111 in a PCIe Application (SMBus Slave Mode)
    • ENSMB = H
    • RXDET = Float
    • PWDN = System control (Hold HIGH until Register Write process is completed)

Table 13. PCIe RX-Detect Programming Sequence

STEP SMBus
REGISTER ADDRESS		 REGISTER DATA (Hex) COMMENTS
1 0x08 0x08 Give RXDET control to SMBus Registers
2 0x0E 0x04 or 0x08 Channel A:
0x04: Auto RX-Detect, outputs test every 12 ms for 600 ms then stops; termination is Hi-Z until RX detection; once detected input termination is 50 Ω

0x08: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until RX detection; once detected input termination is 50 Ω

3 0x15 0x04 or 0x08 Channel B:
0x04: Auto RX-Detect, outputs test every 12 ms for 600 ms then stops; termination is Hi-Z until RX detection; once detected input termination is 50 Ω

0x08: Auto RX-Detect, outputs test every 12 ms until detection occurs; termination is Hi-Z until RX detection; once detected input termination is 50 Ω

4 0x06 0x18 Enable SMBus register control.
Register updates in Steps 1-3 are applied to high speed channels.
  • Pin Settings for DS125BR111 in a PCIe Application (SMBus Master Mode - EEPROM Configuration)
    • ENSMB = Float
    • RXDET = Float
    • PWDN = System control (Hold PWDN HIGH until DONE = 0, EEPROM Write process is completed)

The highlighted bits for RXDET in the Table 6 show the equivalent RXDET control locations to the SMBus Register write sequence shown in Table 13.

9.2 Typical Application

SAS-3 specifications have fully specified Rx-Tx training as a means to establish and optimize signal conditioning settings at the 12.0 Gbps data-rate. The DS125BR111 works to extend the reach possible by adding active linear equalization to the channel, boosting attenuated signals so that they can be more easily recovered at the SAS-3 Rx. The outputs are specially designed to be transparent to TX FIR signaling passing this information critical for optimal link training to the SAS-3 Rx. The typical device settings used in most SAS-3 environments are EQ = Level 4, VOD_DB = 0 and VOD_SEL = 1 in Pin mode or EQ = 0x03, VOD = 111'b, and VOD_DB = 000'b in SMBus mode.

The maximum channel attenuation for a single DS125BR111 in a SAS-3 application utilizing link training is -34 dB @ 6 GHz. Other system variables such as crosstalk and channel topology can have an impact on the link extension possible using the DS125BR111.

111sch_sas.gifFigure 9. DS125BR111 Typical Application

9.2.1 Design Requirements

As with any high speed design, there are many factors which influence the overall performance, this section lists some critical areas for consideration and study.

  • Limit the maximum attenuation to -34 dB @ 6 GHz for the entire channel.
  • Utilize 100 Ω impedance traces. Generally these are very loosely coupled to ease routing length differences.
  • Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
  • The maximum body size for AC-coupling capacitors is 0402.
  • Back-drill connector vias and signal vias to minimize stub length
  • Use Reference plane vias to ensure a low inductance path for the return current.

9.2.2 Detailed Design Procedure

The DS125BR111 is designed to be placed almost anywhere within the channel, maximum channel extension requires the DS125BR111 be placed with attenuation of at least 10 dB on its inputs. The device settings used in a SAS-3 environment are EQ = Level 4, VOD_SEL = 1, and VOD_DB = 0 in Pin mode or EQ = 0x03, VOD = 110'b or 111'b, and VOD_DB = 000'b in SMBus mode. This setting has proven to give the best overall SAS-3 extension for all configurations tested.

9.2.3 Application Curves

5in ds 12g.png
A.
DS125BR111 settings: EQ = 0x01, VOD = 110'b, VOD_DB = 000'b
Figure 10. TLine = 5 Inch 5–Mil FR4 Trace, 12 Gbps