ZHCSBP5C september   2013  – october 2020 SN65DSI86

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Description (continued)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 MIPI Dual DSI Interface
      2. 8.3.2 Embedded DisplayPort Interface
      3. 8.3.3 General-Purpose Input and Outputs
        1. 8.3.3.1 GPIO REFCLK and DSIA Clock Selection
        2. 8.3.3.2 Suspend Mode
        3. 8.3.3.3 Pulse Width Modulation (PWM)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset Implementation
      2. 8.4.2 Power-Up Sequence
      3. 8.4.3 Power Down Sequence
      4. 8.4.4 Display Serial Interface (DSI)
        1. 8.4.4.1 DSI Lane Merging
        2. 8.4.4.2 DSI Supported Data Types
        3. 8.4.4.3 Generic Request Datatypes
          1. 8.4.4.3.1 Generic Read Request 2-Parameters Request
          2. 8.4.4.3.2 Generic Short Write 2-Parameters Request
          3. 8.4.4.3.3 Generic Long Write Packet Request
        4. 8.4.4.4 DSI Pixel Stream Packets
        5. 8.4.4.5 DSI Video Transmission Specifications
        6. 8.4.4.6 Video Format Parameters
        7. 8.4.4.7 GPU LP-TX Clock Requirements
      5. 8.4.5 DisplayPort
        1. 8.4.5.1  HPD (Hot Plug/Unplug Detection)
        2. 8.4.5.2  AUX_CH
          1. 8.4.5.2.1 Native Aux Transactions
        3. 8.4.5.3  I2C-Over-AUX
          1. 8.4.5.3.1 Direct Method (Clock Stretching)
          2. 8.4.5.3.2 Indirect Method (CFR Read/Write)
        4. 8.4.5.4  DisplayPort PLL
        5. 8.4.5.5  DP Output VOD and Pre-emphasis Settings
        6. 8.4.5.6  DP Main Link Configurability
        7. 8.4.5.7  DP Main Link Training
          1. 8.4.5.7.1 Manual Link Training
          2. 8.4.5.7.2 Fast Link Training
          3. 8.4.5.7.3 54
          4. 8.4.5.7.4 Semi-Auto Link Training
          5. 8.4.5.7.5 Redriver Semi-Auto Link Training
        8. 8.4.5.8  Panel Size vs DP Configuration
        9. 8.4.5.9  Panel Self Refresh (PSR)
        10. 8.4.5.10 Secondary Data Packet (SDP)
        11. 8.4.5.11 Color Bar Generator
        12. 8.4.5.12 DP Pattern
          1. 8.4.5.12.1 HBR2 Compliance Eye
          2. 8.4.5.12.2 80-Bit Custom Pattern
        13. 8.4.5.13 BPP Conversion
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface Overview
    6. 8.6 Register Map
      1. 8.6.1 Standard CFR Registers (PAGE 0)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 1080p (1920x1080 60 Hz) Panel
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 eDP Design Procedure
          2. 9.2.1.2.2 76
          3. 9.2.1.2.3 DSI Design Procedure
          4. 9.2.1.2.4 78
          5. 9.2.1.2.5 Example Script
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
    1. 10.1 VCC Power Supply
    2. 10.2 VCCA Power supply
    3. 10.3 VPLL and VCCIO Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DSI Guidelines
      2. 11.1.2 eDP Guidelines
      3. 11.1.3 Ground
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

In order to support the panel stream bit rate, the SN65DSI86 eDP interface must be programmed so that the total eDP data rate is greater than the stream bit rate. In this example, the total eDP data rate is calculated as:

eDP Total Bit Rate = #_of_eDP_Lanes × DataRate × 0.80
eDP Total Bit Rate = 2 × 2.7 Gbps × 0.80
eDP Total Bit Rate = 4.32 Gbps.

In this example, the eDP panel DPCD registers indicates eDP1.3 compliant, supports a data rate of 2.7 Gbps per lane, and a lane count of 2. For this panel to operate properly, the SN65DSI86 would need to be programmed to enable two lanes at a data rate of 2.7 Gbps each.

In portable and mobile applications, total power consumption is a key care-about. In this example, the panel chosen is eDP 1.3 compliant and supports a data rate of 2.7 Gbps per lane. The SN65DSI86 power consumption is a function of the data rate and number of active DP lanes. By reducing the number of active lanes and/or data rate, the total power consumption of the SN65DSI86 is reduced as well. If a panel which supported data rate of 5.4 Gbps was chosen over the example panel, the number of lanes could be reduced from two lanes to one lane. Or if a panel which was eDP1.4 compliant and support 2.43 Gbps data rate was chosen over the example panel, the data rate could be reduced from 2.7 Gbps to 2.43 Gbps.

Once the eDP interface parameters are known, the video resolution parameters required by the panel need to be programmed into the SN65DSI86. For this example, the parameters programmed would be the following:

Horizontal Active = 1920 or 0x780
CHA_ACTIVE_LINE_LENGTH_LOW = 0x80
CHA_ACTIVE_LINE_LENGTH_HIGH = 0x07
Vertical Active = 1080 or 0x438
CHA_VERTICAL_DISPLAY_SIZE_LOW = 0x38
CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0x04
Horizontal Pulse Width = 44 or 0x2C
HORIZONTAL_PULSE_WIDTH_LOW = 0x2C
HORIZONTAL_PULSE_WIDTH_HIGH = 0x00
Vertical Pulse Width = 5
VERTICAL_PULSE_WIDTH_LOW = 0x05
VERTICAL_PULSE_WIDTH_HIGH = 0x00
Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth)
Horizontal Backporch = 280 – (88 + 44)
CHA_HORIZONTAL_BACK_PORCH = 0x94
Horizontal Backporch = 148 or 0x94
Vertical Backporch = VerticalBlanking – (VerticalSyncOffset + VerticalSyncPulseWidth)
Vertical Backporch = 45 – (4 + 5)
Vertical Backporch = 36 or 0x24
CHA_VERTICAL_BACK_PORCH = 0x24
Horizontal Frontporch = HorizontalSyncOffset
Horizontal Frontporch = 88 or 0x58
CHA_HORIZONTAL_FRONT_PORCH = 0x58
Vertical Frontporch = VerticalSyncOffset
Vertical Frontporch = 4
CHA_VERTICAL_FRONT_PORCH = 0x04