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  • SN65HVD82 稳健耐用型 RS-485 收发器

    • ZHCSAC4B October   2012  – November 2017 SN65HVD82

      PRODUCTION DATA.  

  • CONTENTS
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  • SN65HVD82 稳健耐用型 RS-485 收发器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Low-Power Standby Mode
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Configuration
      2. 9.1.2 Bus - Design
      3. 9.1.3 Cable-Length Versus Data Rate
      4. 9.1.4 Stub - Length
      5. 9.1.5 3-V to 5-V Interface
      6. 9.1.6 Noise Immunity
      7. 9.1.7 Transient Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Isolated Bus Node Design
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Design and Layout Considerations For Transient Protection
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 使用 WEBENCH® 工具定制设计方案
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

SN65HVD82 稳健耐用型 RS-485 收发器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 总线 I/O 保护
    • ±16kV 人体模型 (HBM) 保护
    • ±12kV IEC 61000-4-2 接触放电
    • +4kV IEC61000-4-4 快速瞬态突发
  • 工业温度范围:-40°C 至 85°C
  • 用于噪声抑制的较大接收器滞后(典型值为 60mV)
  • 低功耗
    • <1µA 待机电流
    • <1mA 静态电流
  • 信号传输速率经优化高达 250kbps
  • 借助 WEBENCH® 电源设计器,使用 SN65HVD82 创建定制设计方案

2 应用

  • 电表
  • 楼宇自动化
  • 工业网络
  • 安全电子器件

3 说明

该器件兼具驱动器和接收器功能,稳健耐用,可满足特定工业 应用中的严格要求。这些总线引脚可耐受 ESD 事件,并且具备符合人体模型、气隙放电和接触放电规范的高水平保护。

该器件将差分驱动器与差分接收器相结合,共同由单个 5V 电源供电。驱动器差分输出和接收器差分输入在内部连接,构成一个适用于半双工(两线制总线)通信的总线端口。该器件 具有 宽共模电压范围,因此适用于长线缆上的 多点 应用。该器件的额定温度范围介于 -40°C 和 85°C 之间。

器件信息(1)

器件型号 封装 封装尺寸(标称值)
SN65HVD82 SOIC (8) 4.90mm x 3.91mm
  1. 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。

逻辑图(正逻辑)

SN65HVD82 logic_diag_llsed6.gif

4 修订历史记录

Changes from A Revision (July 2015) to B Revision

  • 已将 WEBENCH 链接添加至数据表Go
  • Changed pin 6 From: B To: A and pin 7 From: A To: B in Figure 19 Go

Changes from * Revision (October 2012) to A Revision

  • Added 引脚配置和功能部分,ESD 额定值表,特性 描述 部分,器件功能模式,应用和实施部分,电源相关建议部分,布局部分,器件和文档支持部分以及机械、封装和可订购信息部分Go

5 Pin Configuration and Functions

D Package
16-Pin SOIC
(Top View)
SN65HVD82 po_llsed6.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
A 6 Bus input/output Driver output or receiver input (complementary to B)
B 7 Bus input/output Driver output or receiver input (complementary to A)
D 4 Digital input Driver data input
DE 3 Digital input Driver enable, active high
GND 5 Reference potential Local device ground
R 1 Digital output Receive data output
RE 2 Digital input Receiver enable, active low
VCC 8 Supply 4.5-V to 5.5-V supply

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
VCC Supply voltage –0.5 7 V
Voltage range at A or B Inputs –18 18 V
Input voltage range at any logic pin –0.3 5.7 V
Voltage input range, transient pulse, A and B, through 100Ω –100 100 V
Receiver output current –24 24 mA
TJ Junction temperature 170 °C
Continuous total power dissipation See Thermal Information
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
Machine model (MM), JEDEC Standard 22 ±400
IEC 61000-4-2 ESD (Contact Discharge) Bus terminals and GND ±12000
IEC 60749-26 ESD (Human Body Model) Bus terminals and GND ±16000
IEC 61000-4-4 EMC (Fast Transient Burst Immunity) Bus terminals and GND ±4000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VI Input voltage at any bus terminal (separately or common mode)(1) –7 12 V
VIH High-level input voltage (D, DE and RE inputs) 2 VCC V
VIL Low-level input voltage (D, DE and RE inputs) 0 0.8 V
VID Differential input voltage (A and B inputs) –12 12 V
IO Output current, Driver –60 60 mA
Output current, Receiver –8 8 mA
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
1/tUI Signaling rate 250 kbps
TA Operating free-air temperature (see Application and Implementation section for thermal information) –40 85 °C
TJ Junction Temperature –40 150 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

6.4 Thermal Information

THERMAL METRIC(1) SN65HVD82 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 116.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 60.8 °C/W
RθJB Junction-to-board thermal resistance 57.1 °C/W
ψJT Junction-to-top characterization parameter 13.9 °C/W
ψJB Junction-to-board characterization parameter 56.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VOD| Driver differential output voltage magnitude See Figure 5, RL = 60 Ω, 375 Ω on each output to –7 V to 12 V 1.5 V
RL = 54 Ω (RS-485) See Figure 6 1.5 2 V
RL = 100 Ω (RS-422) 2 2.5 V
Δ|VOD| Change in magnitude of driver differential output voltage RL = 54 Ω, CL = 50 pF See Figure 6 –0.2 0 0.2 V
VOC(SS) Steady-state common-mode output voltage Center of two 27-Ω load resistors See Figure 6 1 VCC/2 3 V
ΔVOC Change in differential driver output common-mode voltage –0.2 0 0.2 V
VOC(PP) Peak-to-peak driver common-mode output voltage 850 mV
COD Differential output capacitance 8 pF
VIT+ Positive-going receiver differential input voltage threshold See (1) –70 -20 mV
VIT– Negative-going receiver differential input voltage threshold –200 –150 See (1) mV
VHYS Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) 40 60 mV
VOH Receiver high-level output voltage IOH = -8 mA 4 VCC–0.3 V
VOL Receiver low-level output voltage IOL = 8 mA 0.2 0.4 V
II Driver input, driver enable, and receiver enable input current –2 2 μA
IOZ Receiver output high-impedance current VO = 0 V or VCC, RE at VCC –10 10 µA
IOS Driver short-circuit output current | IOS | with VA or VB from –7 V to +12 V 150 mA
II Bus input current (disabled driver) VCC = 4.5 to 5.5 V or VCC = 0 V,
DE at 0 V
VI = 12 V 75 125 μA
VI = –7 V –100 –40
ICC Supply current (quiescent) Driver and Receiver enabled DE = VCC, RE=GND,
No load
900 μA
Driver enabled, receiver disabled DE = VCC, RE = VCC,
No load
650
Driver disabled, receiver enabled DE = GND, RE = GND,
No load
650
Driver and receiver disabled DE = GND, D=GND,
RE = VCC, No load
0.4 2
Supply current (dynamic) See Typical Characteristics
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT-.

6.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRIVER
tr, tf Driver differential output rise/fall time RL = 54 Ω, CL = 50 pF, See Figure 7 400 700 1200 ns
tPHL, tPLH Driver propagation delay 90 700 1000 ns
tSK(P) Driver pulse skew, |tPHL – tPLH| 25 200 ns
tPHZ, tPLZ Driver disable time See Figure 8 and Figure 9 50 500 ns
tPZH, tPZL Driver enable time Receiver enabled 500 1000 ns
Receiver disabled 3 9 μs
RECEIVER
tr, tf Receiver output rise/fall time CL = 15 pF, See Figure 10 18 30 ns
tPHL, tPLH Receiver propagation delay time 85 195 ns
tSK(P) Receiver pulse skew, |tPHL – tPLH| 1 15 ns
tPLZ, tPHZ Receiver disable time 50 500 ns
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time Driver enabled, See Figure 11 20 130 ns
Driver disabled, See Figure 12 2 8 μs

6.7 Typical Characteristics

SN65HVD82 C003_SLLSED6.gif Figure 1. Driver Output Voltage vs Driver Output Current
SN65HVD82 C001_SLLSED6.gif Figure 3. Supply Current vs Signaling Rate
SN65HVD82 C002_SLLSED6.gif Figure 2. Driver Rise and Fall Time vs Temperature
SN65HVD82 C004_SLLSED6.gif Figure 4. Receiver Output vs Differential Input Voltage

7 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.

SN65HVD82 s0301-01_llsE11.gif Figure 5. Measurement of Driver Differential Output Voltage With Common-Mode Load
SN65HVD82 s0302-01_llsE11.gif Figure 6. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
SN65HVD82 pmi_dr_sw_llsE11.gif Figure 7. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
SN65HVD82 s0304-01_llsE11.gif
D at 3V to test non-inverting output, D at 0V to test inverting output.
Figure 8. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
SN65HVD82 s0305-01_llsE11.gif
D at 0V to test non-inverting output, D at 3V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
SN65HVD82 s0306-01_llsE11.gif Figure 10. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
SN65HVD82 s0307-01_llsE11.gif Figure 11. Measurement of Receiver Enable/Disable Times With Driver Enabled
SN65HVD82 s0308-01_llsE11.gif Figure 12. Measurement of Receiver Enable Times With Driver Disabled

8 Detailed Description

8.1 Overview

The SN65HVD82 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 250 kbps over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high level of internal transient protection, making it able to withstand up ESD strikes up to 12 kV (per IEC 61000-4-2) and EFT transients up to 4 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of SN65HVD82 may share a common RS-485 bus due to the device’s low bus input currents. The device also features a low standby current consumption of 400 nA (typical).

8.2 Functional Block Diagram

SN65HVD82 logic_diag_llsed6.gif Figure 13. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Receiver Failsafe

The differential receiver is failsafe to invalid bus states caused by:

  • open bus conditions such as a disconnected connector
  • shorted bus conditions such as cable damage shorting the twisted-pair together, or
  • idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential.  In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than –200 mV.  The receiver parameters which determine the failsafe performance are VIT+ and VIT– and VHYS.  As seen in the Electrical Characteristics table, differential signals more negative than
–200 mV will always cause a Low receiver output.  Similarly, differential signals more positive than 200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High.  Only when the differential input is more negative than VIT– will the receiver output transition to a Low state.  So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.

Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring no spurious bits.

8.3.2 Low-Power Standby Mode

When both the driver and receiver are disabled (DE transitions to a low state and RE transitions to a high state) the device enters standby mode. If the enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode. This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.

8.4 Device Functional Modes

Table 1. Driver Function Table

INPUT ENABLE OUTPUTS
D DE A B
H H H L Actively drive bus High
L H L H Actively drive bus Low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus High by default

Table 2. Receiver Function Table

DIFFERENTIAL INPUT ENABLE OUTPUT
VID = VA – VB RE R
VIT+ < VID L H Receive valid bus High
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus Low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output
SN65HVD82 inp-outp_llsed6.gif Figure 14. Equivalent Input and Output Schematic Diagrams

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Device Configuration

The SN65HVD82 is a half-duplex, 250-kbps, RS-485 transceiver operating from a single 5-V supply. The driver and receiver enable pins allow for the configuration of different operating modes.

SN65HVD82 trans_app_llse11.gif Figure 15. SN65HVD82 Transceiver Configurations

Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be turned on and off individually. While this configuration requires two control lines, it allows for selective listening into the bus traffic, whether the driver is transmitting data or not.

Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal. Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device operates as a receiver.

Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only. In this configuration a node not only receives the data from the bus, but also the data it sends and thus can verify that the correct data have been transmitted.

9.1.2 Bus – Design

An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length.

SN65HVD82 ntwrk_app_llse11.gif Figure 16. Typical RS-485 Network with SN65HVD82 Transceivers

Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and proper RS-485 cable with Z0 = 120 Ω.

Line measurements have shown that making RT by up to 10% larger than Z0 improves signal quality. Typical cable sizes are AWG 22 and AWG 24.

The theoretical maximum bus length is assumed with 4000 ft or 1200 m, and represents the length of an AWG 24 cable whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half or 6 dB.

The theoretical maximum number of bus nodes is determined by the ratio of the RS-485 specified maximum of 32 unit loads (UL) and the actual unit load of the applied transceiver. For example, the SN65HVD82 is a 1/8 UL transceiver. Dividing 32 UL by 1/8 UL yields 256 transceivers that can be connected to one bus.

9.1.3 Cable-Length Versus Data Rate

There is an inverse relationship between data rate and cable length. That is, the higher the data rate the shorter the cable and conversely the lower the data rate the longer the cable. While most RS-485 systems utilize data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of up to 250 kbps even at distances of 4000 feet and above. This is possible by allowing for small signal jitter of up to 5 or 10%.

SN65HVD82 cab_length_llsed6.gif Figure 17. Cable Length vs Data Rate Characteristic

9.1.4 Stub – Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. The reason for this is that a stub presents a non-terminated piece of bus line which can introduce reflections if too long. As a rule of thumb the electrical length or round-trip delay of a stub should be less than one tenth of the driver’s rise time, thus leading to a maximum physical stub length of: LStub ≤ 0.1 × tr × v × c, with tr as the driver’s 10/90 rise time, c as the speed of light (3 × 108 m/s or 9.8 × 108 ft/s), and v as the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c.

Thus, for the SN65HVD82 with a minimum rise time of 400 ns the maximum cable stub length yields LStub ≤ 0.1 × 400 × 10-9 × 3 108 × 0.78 = 9.4 m or 30.6 ft.

SN65HVD82 stub_length_llsed6.gif Figure 18. Stub Length

9.1.5 3-V to 5-V Interface

Interfacing the SN65HVD82 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept 3-V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must be level-shifted via a Schottky diode and a 10-kV resistor to connect to the controller input. When R is high, the diode is reverse biased and the controller supply potential lies at the controller input. When R is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the controller input.

SN65HVD82 3v-5v_interface_llsed6.gif Figure 19. 3 V – 5 V Interface

9.1.6 Noise Immunity

The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, VID, is greater than +200 mV, the receiver output turns high, for VID ≤ 200 mV the receiver outputs low. Bus voltages in between these levels can cause the receiver output to go high, or low, or even toggle between logic states. Small bus voltages however occur every time during the bus access hand-off from one driver to the next as the low-impedance termination resistors reduce the bus voltage to zero. To prevent receiver output toggling during bus idling, and thus increasing noise immunity, external bias resistors must be applied to create a bus voltage that is greater than the input sensitivity plus any expected differential noise.

SN65HVD82 noise_app_llsed6.gif Figure 20. SN65HVD82 Noise Immunity

The SN65HVD82 transceiver circumvents idle-bus and differential noise issues by providing a positive input threshold of –20 mV and a typical hysteresis of 60 mV. In the case of an idle-bus condition therefore, a differential noise voltage of up to 160 mVPP can be present without causing the receiver output to change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias resistors and allows for long haul data transmissions in noisy environment.

9.1.7 Transient Protection

The bus terminals of the SN65HVD82 transceiver family possess on-chip ESD protection against ±15 kV human body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC-model produce significantly higher discharge currents than the HBM-model.

SN65HVD82 HBM_app_llse11.gif Figure 21. HBM and IEC-ESD Models and Currents in Comparison

EFTs are usually caused by relay contact bounce or the interruption of inductive loads, while surge transients often results from lightning strikes (direct strike or induced voltages and currents due to an indirect strike), or the switching of power systems including load changes and short circuits switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems.

Figure 22 compares the pulse-power of the EFT and surge transients with the power caused by an IEC-ESD transient. As can be seen the tiny blue blip in the bottom left corner of the left diagram represents the power of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike and certainly against the 500-V surge transient. This type of transient power is well representative for factory environments in industrial and process automation. The right diagram compares the enormous power of a 6-kV surge transient, which more likely occurs in e-metering applications of power generating and power grid systems, with the aforementioned 500-V surge transient. Note that the unit of the pulse-power changes from kW to MW, thus making the power of the 500-V surge transient almost dropping off the scale.

SN65HVD82 power_comp_llsed6.gif Figure 22. Power Comparison of ESD, EFT, and Surge Transients

In the case of surge transients, their long pulse duration and slowly decreasing pulse power signifies high energy content.

The electrical energy of a transient that is dumped onto the transceiver’s internal protections cells is converted into thermal energy, or heat that literally fries the protection cells, thus destroying the transceiver. Figure 23 showcases the large differences in transient energies for single ESD, EFT, and surge transients as well as for an EFT pulse train, commonly applied during compliance testing.

SN65HVD82 comp_trans_llsed6.gif Figure 23. Comparison of Transient Energies

Figure 24 suggests two circuit designs providing protection against surge transients. Table 3 presents the associated bill of material.

Table 3. Bill of Materials

DEVICE FUNCTION ORDER NUMBER MANUFACTURER
XCVR 3.3V, 250kbps RS-485 Transceiver SN65HVD82D TI
R1,R2 10Ω, Pulse-Proof Thick-Film Resistor CRCW0603010RJNEAHP Vishay
TVS Bidirectional 400W Transient Suppressor CDSOT23-SM712 Bourns
TBU1,TBU2 Bidirectional. 200mA Transient Blocking Unit TBU-CA-065-200-WH Bourns
MOV1,MOV2 200V, Metal-Oxide Varistor MOV-10D201K Bourns
SN65HVD82 prot_app_llse11.gif Figure 24. Transient Protection Against ESD, EFT, and Surge Transients

Both circuits are designed for 10-kV ESD and 4-kV EFT transient protection. The left however provides surge protection of ≥ 500-V transients only, while the right protection circuits can withstand 5-kV surge transients.

9.2 Typical Application

SN65HVD82 iso_app_llsed6.gif Figure 25. Isolated Bus Node With Transient Protection

9.2.1 Design Requirements

The following list outlines sample design requirements for the typical application example found in Figure 25

  • RS-485-compliant bus interface (needs differential signal amplitude of at least 1.5 V under fully-loaded conditions – essentially, maximum number of nodes connected and with dual 120-Ω termination).
  • Galvanic isolation of both signal and power supply lines.
  • Able to withstand ESD transients up to 10 kV (per IEC 61000-4-2) and EFTs up to 4 kV (per IEC 61000-4-4).
  • Full control of data flow on bus in order to prevent contention (for half-duplex communication).

9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the SN65HVD82 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

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9.2.2.2 Isolated Bus Node Design

Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to the bus transceiver via a multi-channel, digital isolator (Figure 25).

Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TPS76350

Signal isolation utilizes the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are pulled-up via 4.7-kΩ resistors to limit their input currents during transient events.

While the transient protection is similar to the one in Figure 24 (left circuit), an additional high-voltage capacitor is used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This is necessary as noise transients on the bus are usually referred to Earth potential.

RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to prevent charging of the floating ground to dangerous potentials during normal operation.

Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if it is expected that fast transients might charge CHV to high-potentials.

Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire connecting this island to PE ground at the entrance of the power supply unit (PSU).

In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are connecting to the chassis at the other end.

9.2.3 Application Curve

SN65HVD82 app_curve1_sllsed6.gif Figure 26. SN65GVD82 D Input (Top), Differential Output (Middle), and R Output (Bottom), 250 kbps Operation, PRBS Data Pattern

 

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