该器件兼具驱动器和接收器功能,稳健耐用,可满足特定工业 应用中的严格要求。这些总线引脚可耐受 ESD 事件,并且具备符合人体模型、气隙放电和接触放电规范的高水平保护。
该器件将差分驱动器与差分接收器相结合,共同由单个 5V 电源供电。驱动器差分输出和接收器差分输入在内部连接,构成一个适用于半双工(两线制总线)通信的总线端口。该器件 具有 宽共模电压范围,因此适用于长线缆上的 多点 应用。该器件的额定温度范围介于 -40°C 和 85°C 之间。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
SN65HVD82 | SOIC (8) | 4.90mm x 3.91mm |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
A | 6 | Bus input/output | Driver output or receiver input (complementary to B) |
B | 7 | Bus input/output | Driver output or receiver input (complementary to A) |
D | 4 | Digital input | Driver data input |
DE | 3 | Digital input | Driver enable, active high |
GND | 5 | Reference potential | Local device ground |
R | 1 | Digital output | Receive data output |
RE | 2 | Digital input | Receiver enable, active low |
VCC | 8 | Supply | 4.5-V to 5.5-V supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage | –0.5 | 7 | V |
Voltage range at A or B Inputs | –18 | 18 | V | |
Input voltage range at any logic pin | –0.3 | 5.7 | V | |
Voltage input range, transient pulse, A and B, through 100Ω | –100 | 100 | V | |
Receiver output current | –24 | 24 | mA | |
TJ | Junction temperature | 170 | °C | |
Continuous total power dissipation | See Thermal Information | |||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | ||||
Machine model (MM), JEDEC Standard 22 | ±400 | ||||
IEC 61000-4-2 ESD (Contact Discharge) | Bus terminals and GND | ±12000 | |||
IEC 60749-26 ESD (Human Body Model) | Bus terminals and GND | ±16000 | |||
IEC 61000-4-4 EMC (Fast Transient Burst Immunity) | Bus terminals and GND | ±4000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 4.5 | 5 | 5.5 | V | |
VI | Input voltage at any bus terminal (separately or common mode)(1) | –7 | 12 | V | ||
VIH | High-level input voltage (D, DE and RE inputs) | 2 | VCC | V | ||
VIL | Low-level input voltage (D, DE and RE inputs) | 0 | 0.8 | V | ||
VID | Differential input voltage (A and B inputs) | –12 | 12 | V | ||
IO | Output current, Driver | –60 | 60 | mA | ||
Output current, Receiver | –8 | 8 | mA | |||
RL | Differential load resistance | 54 | 60 | Ω | ||
CL | Differential load capacitance | 50 | pF | |||
1/tUI | Signaling rate | 250 | kbps | |||
TA | Operating free-air temperature (see Application and Implementation section for thermal information) | –40 | 85 | °C | ||
TJ | Junction Temperature | –40 | 150 | °C |
THERMAL METRIC(1) | SN65HVD82 | UNIT | |
---|---|---|---|
D (SOIC) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 116.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 60.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 57.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 13.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
|VOD| | Driver differential output voltage magnitude | See Figure 5, RL = 60 Ω, 375 Ω on each output to –7 V to 12 V | 1.5 | V | ||||
RL = 54 Ω (RS-485) | See Figure 6 | 1.5 | 2 | V | ||||
RL = 100 Ω (RS-422) | 2 | 2.5 | V | |||||
Δ|VOD| | Change in magnitude of driver differential output voltage | RL = 54 Ω, CL = 50 pF | See Figure 6 | –0.2 | 0 | 0.2 | V | |
VOC(SS) | Steady-state common-mode output voltage | Center of two 27-Ω load resistors | See Figure 6 | 1 | VCC/2 | 3 | V | |
ΔVOC | Change in differential driver output common-mode voltage | –0.2 | 0 | 0.2 | V | |||
VOC(PP) | Peak-to-peak driver common-mode output voltage | 850 | mV | |||||
COD | Differential output capacitance | 8 | pF | |||||
VIT+ | Positive-going receiver differential input voltage threshold | See (1) | –70 | -20 | mV | |||
VIT– | Negative-going receiver differential input voltage threshold | –200 | –150 | See (1) | mV | |||
VHYS | Receiver differential input voltage threshold hysteresis (VIT+ – VIT–) | 40 | 60 | mV | ||||
VOH | Receiver high-level output voltage | IOH = -8 mA | 4 | VCC–0.3 | V | |||
VOL | Receiver low-level output voltage | IOL = 8 mA | 0.2 | 0.4 | V | |||
II | Driver input, driver enable, and receiver enable input current | –2 | 2 | μA | ||||
IOZ | Receiver output high-impedance current | VO = 0 V or VCC, RE at VCC | –10 | 10 | µA | |||
IOS | Driver short-circuit output current | | IOS | with VA or VB from –7 V to +12 V | 150 | mA | ||||
II | Bus input current (disabled driver) | VCC = 4.5 to 5.5 V or VCC = 0 V, DE at 0 V |
VI = 12 V | 75 | 125 | μA | ||
VI = –7 V | –100 | –40 | ||||||
ICC | Supply current (quiescent) | Driver and Receiver enabled | DE = VCC, RE=GND, No load |
900 | μA | |||
Driver enabled, receiver disabled | DE = VCC, RE = VCC, No load |
650 | ||||||
Driver disabled, receiver enabled | DE = GND, RE = GND, No load |
650 | ||||||
Driver and receiver disabled | DE = GND, D=GND, RE = VCC, No load |
0.4 | 2 | |||||
Supply current (dynamic) | See Typical Characteristics |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DRIVER | |||||||
tr, tf | Driver differential output rise/fall time | RL = 54 Ω, CL = 50 pF, See Figure 7 | 400 | 700 | 1200 | ns | |
tPHL, tPLH | Driver propagation delay | 90 | 700 | 1000 | ns | ||
tSK(P) | Driver pulse skew, |tPHL – tPLH| | 25 | 200 | ns | |||
tPHZ, tPLZ | Driver disable time | See Figure 8 and Figure 9 | 50 | 500 | ns | ||
tPZH, tPZL | Driver enable time | Receiver enabled | 500 | 1000 | ns | ||
Receiver disabled | 3 | 9 | μs | ||||
RECEIVER | |||||||
tr, tf | Receiver output rise/fall time | CL = 15 pF, See Figure 10 | 18 | 30 | ns | ||
tPHL, tPLH | Receiver propagation delay time | 85 | 195 | ns | |||
tSK(P) | Receiver pulse skew, |tPHL – tPLH| | 1 | 15 | ns | |||
tPLZ, tPHZ | Receiver disable time | 50 | 500 | ns | |||
tPZL(1), tPZH(1)
tPZL(2), tPZH(2) |
Receiver enable time | Driver enabled, See Figure 11 | 20 | 130 | ns | ||
Driver disabled, See Figure 12 | 2 | 8 | μs |
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec, output impedance 50 Ω.
The SN65HVD82 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 250 kbps over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high level of internal transient protection, making it able to withstand up ESD strikes up to 12 kV (per IEC 61000-4-2) and EFT transients up to 4 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of SN65HVD82 may share a common RS-485 bus due to the device’s low bus input currents. The device also features a low standby current consumption of 400 nA (typical).
The differential receiver is failsafe to invalid bus states caused by:
Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT– and VHYS. As seen in the Electrical Characteristics table, differential signals more negative than
–200 mV will always cause a Low receiver output. Similarly, differential signals more positive than 200 mV will always cause a High receiver output.
When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High. Only when the differential input is more negative than VIT– will the receiver output transition to a Low state. So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.
Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring no spurious bits.
When both the driver and receiver are disabled (DE transitions to a low state and RE transitions to a high state) the device enters standby mode. If the enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode. This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.
INPUT | ENABLE | OUTPUTS | ||
---|---|---|---|---|
D | DE | A | B | |
H | H | H | L | Actively drive bus High |
L | H | L | H | Actively drive bus Low |
X | L | Z | Z | Driver disabled |
X | OPEN | Z | Z | Driver disabled by default |
OPEN | H | H | L | Actively drive bus High by default |
DIFFERENTIAL INPUT | ENABLE | OUTPUT | |
---|---|---|---|
VID = VA – VB | RE | R | |
VIT+ < VID | L | H | Receive valid bus High |
VIT– < VID < VIT+ | L | ? | Indeterminate bus state |
VID < VIT– | L | L | Receive valid bus Low |
X | H | Z | Receiver disabled |
X | OPEN | Z | Receiver disabled by default |
Open-circuit bus | L | H | Fail-safe high output |
Short-circuit bus | L | H | Fail-safe high output |
Idle (terminated) bus | L | H | Fail-safe high output |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The SN65HVD82 is a half-duplex, 250-kbps, RS-485 transceiver operating from a single 5-V supply. The driver and receiver enable pins allow for the configuration of different operating modes.
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be turned on and off individually. While this configuration requires two control lines, it allows for selective listening into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal. Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device operates as a receiver.
Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only. In this configuration a node not only receives the data from the bus, but also the data it sends and thus can verify that the correct data have been transmitted.
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer cable length.
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and proper RS-485 cable with Z0 = 120 Ω.
Line measurements have shown that making RT by up to 10% larger than Z0 improves signal quality. Typical cable sizes are AWG 22 and AWG 24.
The theoretical maximum bus length is assumed with 4000 ft or 1200 m, and represents the length of an AWG 24 cable whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half or 6 dB.
The theoretical maximum number of bus nodes is determined by the ratio of the RS-485 specified maximum of 32 unit loads (UL) and the actual unit load of the applied transceiver. For example, the SN65HVD82 is a 1/8 UL transceiver. Dividing 32 UL by 1/8 UL yields 256 transceivers that can be connected to one bus.
There is an inverse relationship between data rate and cable length. That is, the higher the data rate the shorter the cable and conversely the lower the data rate the longer the cable. While most RS-485 systems utilize data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of up to 250 kbps even at distances of 4000 feet and above. This is possible by allowing for small signal jitter of up to 5 or 10%.
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. The reason for this is that a stub presents a non-terminated piece of bus line which can introduce reflections if too long. As a rule of thumb the electrical length or round-trip delay of a stub should be less than one tenth of the driver’s rise time, thus leading to a maximum physical stub length of: LStub ≤ 0.1 × tr × v × c, with tr as the driver’s 10/90 rise time, c as the speed of light (3 × 108 m/s or 9.8 × 108 ft/s), and v as the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c.
Thus, for the SN65HVD82 with a minimum rise time of 400 ns the maximum cable stub length yields LStub ≤ 0.1 × 400 × 10-9 × 3 108 × 0.78 = 9.4 m or 30.6 ft.
Interfacing the SN65HVD82 to a 3-V controller is easy. Because the 5-V logic inputs of the transceiver accept 3-V input signals they can be directly connected to the controller I/O. The 5-V receiver output, R, however must be level-shifted via a Schottky diode and a 10-kV resistor to connect to the controller input. When R is high, the diode is reverse biased and the controller supply potential lies at the controller input. When R is low, the diode is forward biased and conducts. In this case only the diode forward voltage of 0.2 V lies at the controller input.
The input sensitivity of a standard RS-485 transceiver is ±200 mV. When the differential input voltage, VID, is greater than +200 mV, the receiver output turns high, for VID ≤ 200 mV the receiver outputs low. Bus voltages in between these levels can cause the receiver output to go high, or low, or even toggle between logic states. Small bus voltages however occur every time during the bus access hand-off from one driver to the next as the low-impedance termination resistors reduce the bus voltage to zero. To prevent receiver output toggling during bus idling, and thus increasing noise immunity, external bias resistors must be applied to create a bus voltage that is greater than the input sensitivity plus any expected differential noise.
The SN65HVD82 transceiver circumvents idle-bus and differential noise issues by providing a positive input threshold of –20 mV and a typical hysteresis of 60 mV. In the case of an idle-bus condition therefore, a differential noise voltage of up to 160 mVPP can be present without causing the receiver output to change states from high to low. This increased noise immunity eliminates the need for idle-bus failsafe bias resistors and allows for long haul data transmissions in noisy environment.
The bus terminals of the SN65HVD82 transceiver family possess on-chip ESD protection against ±15 kV human body model (HBM) and ±12 kV IEC61000-4-2 contact discharge. As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. The IEC-ESD test is far more severe than the HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD of the IEC-model produce significantly higher discharge currents than the HBM-model.
EFTs are usually caused by relay contact bounce or the interruption of inductive loads, while surge transients often results from lightning strikes (direct strike or induced voltages and currents due to an indirect strike), or the switching of power systems including load changes and short circuits switching. These transients are often encountered in industrial environments, such as factory automation and power-grid systems.
Figure 22 compares the pulse-power of the EFT and surge transients with the power caused by an IEC-ESD transient. As can be seen the tiny blue blip in the bottom left corner of the left diagram represents the power of a 10-kV ESD transient, which already dwarfs against the significantly higher EFT power spike and certainly against the 500-V surge transient. This type of transient power is well representative for factory environments in industrial and process automation. The right diagram compares the enormous power of a 6-kV surge transient, which more likely occurs in e-metering applications of power generating and power grid systems, with the aforementioned 500-V surge transient. Note that the unit of the pulse-power changes from kW to MW, thus making the power of the 500-V surge transient almost dropping off the scale.
In the case of surge transients, their long pulse duration and slowly decreasing pulse power signifies high energy content.
The electrical energy of a transient that is dumped onto the transceiver’s internal protections cells is converted into thermal energy, or heat that literally fries the protection cells, thus destroying the transceiver. Figure 23 showcases the large differences in transient energies for single ESD, EFT, and surge transients as well as for an EFT pulse train, commonly applied during compliance testing.
Figure 24 suggests two circuit designs providing protection against surge transients. Table 3 presents the associated bill of material.
DEVICE | FUNCTION | ORDER NUMBER | MANUFACTURER |
---|---|---|---|
XCVR | 3.3V, 250kbps RS-485 Transceiver | SN65HVD82D | TI |
R1,R2 | 10Ω, Pulse-Proof Thick-Film Resistor | CRCW0603010RJNEAHP | Vishay |
TVS | Bidirectional 400W Transient Suppressor | CDSOT23-SM712 | Bourns |
TBU1,TBU2 | Bidirectional. 200mA Transient Blocking Unit | TBU-CA-065-200-WH | Bourns |
MOV1,MOV2 | 200V, Metal-Oxide Varistor | MOV-10D201K | Bourns |
Both circuits are designed for 10-kV ESD and 4-kV EFT transient protection. The left however provides surge protection of ≥ 500-V transients only, while the right protection circuits can withstand 5-kV surge transients.
The following list outlines sample design requirements for the typical application example found in Figure 25
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Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to the bus transceiver via a multi-channel, digital isolator (Figure 25).
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TPS76350
Signal isolation utilizes the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are pulled-up via 4.7-kΩ resistors to limit their input currents during transient events.
While the transient protection is similar to the one in Figure 24 (left circuit), an additional high-voltage capacitor is used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This is necessary as noise transients on the bus are usually referred to Earth potential.
RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if it is expected that fast transients might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are connecting to the chassis at the other end.