TIDT333 may   2023

 

  1.   Description
  2.   Features
  3.   Applications
  4. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Input and Output Signals
  5. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
    4. 2.4 Bode Plots
  6. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Output Voltage Ripple
    3. 3.3 Short-Circuit Protection
    4. 3.4 Load Transients
    5. 3.5 Start-Up

3.1 Switching

The maximum voltage stress on the drain of the low-side FETs (Q3 and Q4) occurs with 150-V input and 5-A load. This was recorded as 178 Vpk, as shown in the following figure.

GUID-20230427-SS0I-V8WV-XXZL-02QQKPNNK6ZN-low.jpgFigure 3-1 Maximum Voltage Stress