SWRZ149 july   2023 IWRL1432

ADVANCE INFORMATION  

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1. 5.1  ANA #51
    2. 5.2  ANA #52
    3. 5.3  DIG #1
    4. 5.4  DIG #2
    5. 5.5  DIG #3
    6. 5.6  DIG #4
    7. 5.7  DIG #6
    8. 5.8  DIG #7
    9. 5.9  DIG #8
    10. 5.10 DIG #9
    11. 5.11 DIG #10
  7. 6Trademarks
  8.   Revision History

5.8 DIG #7

APPSS Cortex-M4 doesn't get the correct error response when cluster 3 retention memories are accessed in low-power deep-sleep powered down state

Revision(s) Affected

IWRL1432ES1.1

Details

The logic to generate error when Cortex-M4F tries to access cluster 3 memories in powered down state is incorrect due to which Cortex-M4F doesn't get the correct error response.

Workaround

Software shouldn't try to access cluster 3 retention memories during low-power deep-sleep powered down state