SWRZ074C May   2017  – May 2021 IWR1443

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
    2. 4.2 Identification
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#01
    2.     MSS#03A
    3.     MSS#04A
    4.     MSS#05A
    5.     MSS#06
    6.     MSS#07A
    7.     MSS#08
    8.     MSS#09
    9.     MSS#13
    10.     MSS#14
    11.     MSS#15
    12.     MSS#19
    13.     MSS#20
    14.     MSS#21A
    15.     MSS#22
    16.     MSS#23
    17.     MSS#24
    18.     MSS#25
    19.     MSS#26
    20.     MSS#27
    21.     MSS#28
    22.     MSS#29
    23.     MSS#30
    24.     MSS#31
    25.     MSS#32
    26.     MSS#33
    27.     MSS#35
    28.     MSS#37B
    29.     MSS#38A
    30.     MSS#39
    31.     MSS#40
    32.     MSS#43A
    33.     MSS#44
    34.     MSS#45
    35.     ANA#01
    36.     ANA#02
    37.     ANA#03
    38.     ANA#04
    39.     ANA#06
    40.     ANA#07
    41.     ANA#08A
    42.     ANA#10A
    43.     ANA#11A
    44.     ANA#12A
    45.     ANA#13B
    46.     ANA#15
    47.     ANA#16
    48.     ANA#17A
    49.     ANA#18B
    50.     ANA#20
    51.     ANA#21A
    52.     ANA#22A
    53.     ANA#24A
    54.     ANA#27
  7. 7Trademarks
  8. 8Revision History

MSS#35

EDMA TPTC Generates an Incorrect Address on the Read Interface, Causing one or More Data Integrity Failures, Hangs, or Extra Reads

Revision(s) Affected:

IWR1443 ES1.0, IWR1443 ES2.0, and IWR1443 ES3.0

Description:

Certain scenarios could lead to an incorrect read, hang, or data integrity issues in the EDMA TPTC block. Table 6-1 shows the various scenarios and the resulting effects of each scenario.

A scenario happens, if ALL conditions listed for that scenario are satisfied (true); that is, "AND" of all conditions.

A “hang” outcome means that one or more attempts of the hang causing scenarios can progressively lead to not receiving a "transfer completion" indication from the TPTC. The last transfer attempt which does not receive the completion indication can be any transfer – any scenario transfer within this advisory or even outside of this advisory.

Table 6-1 EDMA TPTC Scenario IDs and Condition Results
SCENARIO
ID
CONDITIONS DATA
INTEGRITY
FAILURES
HANGS EXTRA
READS
1 AB-sync
BCNT > 1
ACNT not in [2,4,8,16,32]
(ACNT < 64) OR ((ACNT = 64) AND (SRCBIDX != ACNT))
Source Addressing crossing 4-KB boundary for any of the BCNT number of ACNT transfers.
Yes
(see Figure 6-4)
Possible Possible
2 AB-sync with BCNT=1 or A-sync
ACNT not in [2..24, 32]
ACNT <= 64
Source Addressing crossing 4-KB boundary for any of the BCNT number of ACNT transfers.
No Possible Yes
3 AB-sync with BCNT=1 or A-sync
ACNT in [2..24, 32]
Source Addressing crossing 4-KB boundary for any of the BCNT number of ACNT transfers.
No No Yes
(see Figure 6-1)
4 AB-sync
BCNT > 1
ACNT in [2,4,8,16,32]
SRCBIDX = ACNT
ACNT * BCNT <=64
Source Addressing crossing 4-KB boundary for any of the BCNT number of ACNT transfers.
No No Yes
(see Figure 6-2)
5 AB-sync
BCNT > 1
ACNT in [2,4,8,16,32]
SRCBIDX = ACNT
ACNT * BCNT <=64
Source Addressing does NOT cross 4-KB boundary for any of the BCNT number of ACNT transfers; that is, NOT of
Source Addressing crosses 4-KB boundary for merged source array of size ACNT * BCNT.
No No Yes
(see Figure 6-3)

Source Addressing crossing 4-KB boundary cross condition [1] in Table 6-1 is defined as follows:
[X(i) = LSB_12bits(SRC_ADDR + i * SRC_BIDX)] + ACNT > 0x1000
where 0 <= i < BCNT

Source Addressing crossing 4-KB boundary cross condition [2] in Table 6-1 is defined as follows:
LSB_12bits(SRC_ADDR) + (ACNT * BCNT) > 0x1000

For the and expressions above, note that the SRC_ADDR is candidate source address considering the C-dimension. If CCNT > 1, then, the SRC_ADDR would be every candidate source address for all CCNTs depending on the type of transfer and the SRCCIDX.

For each extra read in Scenario ID #3 for which Condition [1] is applicable, each index i above that satisfies the condition results in extra read from starting address SRC_ADDR + (i + 1) * SRCBIDX and of length equal to the distance from the start address to the boundary [that is, 0x1000 – X(i)]. Note: length < ACNT.

GUID-39446A14-E0F3-45BD-9BED-D93DD7256232-low.png Figure 6-1 Scenario ID #3 – Extra Reads

For each extra read Scenario ID #4 in for which Condition [1] is applicable, there is an extra read from starting address SRC + BCNT * ACNT (=SRCBIDX) of length equal to the distance of the start address to the boundary [that is, length is 0x1000 – X(i)], where i is the index of one and only 4-KB boundary crossing condition. Note: length < ACNT.

GUID-A735DBB7-D94D-4737-932B-6B128BAAD09A-low.png Figure 6-2 Scenario ID #4 – Extra Reads

For the extra read Scenario ID #5 in for which Condition [2] is applicable, there is an extra read from starting address SRC + BCNT * ACNT (=SRCBIDX) of length equal to the distance of the start address and is of length ACNT.

GUID-65DB6C3F-BDB7-4715-A043-9B0B67436DA2-low.png Figure 6-3 Scenario ID #5 – Extra Reads

 

GUID-374011D4-51AC-4285-A88F-09A5C8565BB2-low.png Figure 6-4 Scenario ID #1 – Data Integrity Failure

Workaround(s):

Workaround #1 - ALL SCENARIO IDs (see Table 6-1)

Prevent one or more of the conditions necessary for the problematic scenarios to happen.

Workaround #2 - Scenario ID #3, Scenario ID #4, and Scenario ID #5 (see Table 6-1)– EXTRA READS

For Scenario ID #3, Scenario ID #4, and Scenario ID #5– EXTRA READS, another workaround besides avoiding the 4-KB boundary cross conditions, is to ensure that buffers involved in this kind of transfer are positioned so that extra reads stay within the physical memory boundaries. If the extra reads go to Reserved space or space blocked by the Memory Protection Unit (MPU), the TPTC generates a bus error interrupt to the processor.