This technical reference manual provides information about how to use the CC13x1x3 and CC26x1x3SimpleLink™ ultra-low power wireless microcontroller (MCU). The CC26x1x3 and the CC13x1x3 device platforms share the same MCU architecture and most of the peripherals. The radio in the CC26x1x3 device operates in the 2.4 GHz ISM frequency band while the radio in the CC13x1x3 device is designed for use in the Sub-1 GHz frequency bands. This document covers the whole platform of devices, so refer to the individual device data sheets for supported modules and features.
This document is organized into sections that correspond to each major feature; it explains the features and functionality of each module and how to use them. For each feature, references are provided for the driver documentation of the corresponding operating systems. This document does not contain performance characteristics of the device or modules, which are gathered in the corresponding device data sheets. This manual is intended for system software developers, hardware designers, and application developers.
The CC13x1x3 and
CC26x1x3 device platform includes both 2.4 GHz (CC26x1x3) and
Sub-1 GHz (CC13x1x3) radios along with a variety of different memory sizes, peripherals, and package options. All devices are centered around an Arm®Cortex®-M4 series processor that handles the application layer and protocol stack, as well as an autonomous radio core centered around an Arm® Cortex®-M0 processor that handles all the low-level radio control and processing. Network processor options are available.
The availability of a wide range of different radio and MCU system combinations makes these device families well suited for almost any low-power RF node implementation.
The naming convention applied for a call consists of:
The following related documents are available on the CC13x1x3 and CC26x1x3 device product pages at www.ti.com:
CC1311P3 data sheet and errata (Technical Documents)
CC2651P3 datasheet and errata (Technical Documents)
This list of documents was current as of publication date. Check the website for additional documentation, application notes, and white papers.
Additional, related documentation follows:
Cortex -M4 Devices Generic User Guide (see documentation at Arm.com)
SimpleLink and EnergyTrace are trademarks of Texas Instruments.
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Motorola is a trademark of Motorola Trademark Holdings, LLC.
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Thumb, Arm7, AMBA, and PrimeCell are registered trademarks of Arm Limited (or its subsidiaries).
Zigbee is a registered trademark of Zigbee Alliance.
All trademarks are the property of their respective owners.
The CC13x1x3 and CC26x1x3 device platform of the SimpleLink™ ultra-low-power wireless MCUs provides solutions for a wide range of applications. To help the user develop these applications, this user's guide focuses on the use of the different building blocks of the devices. For detailed device descriptions, complete feature lists, and performance numbers, see the data sheet for the specific device. The following subsections provide easy access to relevant information and guide the reader to the different chapters in this document.
The device platform system-on-chips (SoCs) are optimized for ultra-low power, while providing fast and capable MCU systems to enable short processing times and high integration. The combination of an Arm® Cortex®-M4 processing core up to 48 MHz, flash memory, and a wide selection of peripherals makes the CC13x1x3 and CC26x1x3 device platform specifically designed for single-chip implementation or network processor implementations of lower-power RF nodes.
The CC13x1x3 and CC26x1x3 SimpleLink™ ultra-low-power wireless MCU platform is positioned for low-power wireless applications, such as:
Figure 2-1 shows the building blocks of the CC13x1x3 and CC26x1x3 device platform.
The CC13x1x3 and CC26x1x3 device platform has the following features:
For applications requiring extreme conservation of power, the CC13x1x3 and CC26x1x3 device platform features a power-management system to efficiently power down the devices to a low-power state during extended periods of inactivity. A power-up and power-down sequencer, a 32-bit sleep timer (an RTC), with interrupt and 32 kB of ultra-low-leakage (ULL) RAM with retention in all power modes positions the MCU perfectly for battery applications.
In addition, the CC13x1x3 and CC26x1x3 device platform offers the advantages of the widely available development tools of Arm®, SoC infrastructure IP applications, and a large user community. Additionally, the microcontroller uses Arm Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost.
TI offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network.
The following subsections provide an overview of the features of the CC13x1x3 and CC26x1x3 device platform.
The following subsections provide an overview of the Arm® Cortex®-M4 processor core and instruction set, the integrated system timer (SysTick), and the NVIC.
The CC13x1x3 and CC26x1x3 device platform is designed around an Arm® Cortex®-M4 processor core. The Arm® Cortex®-M4 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
Features of the processor core are as follows:
The Arm® Cortex®-M4 processor includes an integrated system timer (SysTick). SysTick provides a simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways; for example:
The CC13x1x3 and CC26x1x3 device controller includes the Arm® NVIC. The NVIC and Arm® Cortex®-M4 prioritize and handle all exceptions in handler mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to state saving, thus enabling efficient interrupt entry. The processor supports tail-chaining, that is, back-to-back interrupts can be performed without the overhead of state saving and restoration. Software can set eight priority levels on seven exceptions (system handlers) and can set device interrupts.
Features of the NVIC are as follows:
The system control block (SCB) provides system implementation information and system control (configuration, control, and reporting of system exceptions).
The following subsections describe the on-chip memory modules.
The CC13x1x3 and CC26x1x3 device platform provides 32 kB of low-leakage, on-chip SRAM with optional retention in all power modes. Retention can be configured per 16 kB block. Additionally, the 8 kB flash cache RAM can be reconfigured to operate as normal system RAM. Because read-modify-write (RMW) operations are very time consuming, Arm® has introduced bit-banding technology in the Arm® Cortex®-M4 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the micro DMA (µDMA) controller.
The flash block provides an in-circuit, programmable, nonvolatile program memory for the device. The 352 kB of flash memory is organized as a set of 8 kB pages that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These pages can be individually protected. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. In addition to holding program code and constants, the nonvolatile memory allows the application to save data that must be preserved so that it is available after restarting the device. Using this feature lets the user use saved network-specific data to avoid the need for a full start-up and network find-and-join process.
The ROM is preprogrammed with a boot sequence, device driver functions, low-level protocol stack components, and a serial bootloader (SPI or UART).
The CC26x1x3 device provides a highly integrated low-power 2.4 GHz radio transceiver with support for multiple modulations and packet formats. The CC13x1x3 device provides similar functionality optimized for the Sub-1 GHz bands. The radio subsystem provides an interface between the MCU and the radio, which makes it possible to issue commands, read status, also automate and sequence radio events.
The security core of the CC13x1x3 and CC26x1x3 device platform features an Advanced Encryption Standard (AES) module with 128-bit key support, local key storage and DMA capability.
Features of the AES engine are as follows:
General-purpose timers can be used to count or time external events that drive the timer-input pins. Each 16- or 32-bit GPTM block provides two 16-bit timers or counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer.
The general-purpose timer module (GPTM) contains four 16- or 32-bit GPTM blocks with the following functional options:
The watchdog timer is used to regain control when the system fails because of a software error or an external device fails to respond properly. The watchdog timer can generate an interrupt or a reset when a predefined time-out value is reached.