SSZTAH7 january   2017 MSP430F5529 , TPS3110 , TPS3851

 

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    2.     Just What Is a Watchdog Timer?
    3.     Why Are Watchdog Timers So Important?
    4.     How Can I Implement a Watchdog Timer in My Embedded System?
    5.     Additional Resources

Kelvin Odom

Much like a small, yappy dog that lives in a celebrity’s purse, watchdog timers are often considered unnecessary or excessive. To equate the two, how ever, would do a great disservice to the watchdog. Unlike “purse dogs,” watchdogs add critical monitoring features that allow you to internally and externally monitor your system for failure and take action should that happen.

Just What Is a Watchdog Timer?

Simply put, a watchdog timer is a device that asserts a reset output if it has not received a periodic pulse signal from a processor within a specific time frame. One way this is implemented is by a digital signal output (GPIO) from the processor feeding into the watchdog input (WDI) of an external watchdog timer as shown in Figure 1. TPS3851 is a supervisor with an integrated watchdog timer. This allows it to both supervise the supply rail to the microcontroller and monitor the digital pulse emanating from the MCU in an external fashion.

GUID-FE9CA528-0CB1-4D7D-B460-232F3F45C540-low.png Figure 1 Watchdog Monitoring Provided by the TPS3851

The processor periodically sends a pulse to the watchdog timer to indicate that the system software is operating properly. If the watchdog timer does not receive this pulse within an allotted time frame (known as the watchdog timeout), the watchdog timer asserts a reset output. This reset output can be used to notify the system that the processor has experienced a hang or a freeze, or to reset the processor itself. Figure 2 illustrates a pulse received within the watchdog timeout and a pulse received after the watchdog timeout has expired.

GUID-72605D1A-B2ED-445D-91C0-FA81C2C49A91-low.png Figure 2 Operation of a Standard Watchdog Timer

Why Are Watchdog Timers So Important?

Watchdog timers provide a method for alerting a system or resetting a processor whose software has experienced a freeze or hang. While no one purposely designs software to freeze, good system designers plan for failures anyway – as it’s always better to prepare for the unexpected. Without this monitoring, the processor could stay frozen indefinitely and lead to further system failure. An external watchdog timer with an adjustable timeout interval, such as the TPS3851, can identify these software freezes within just a few milliseconds and reset the system or processor appropriately. This functionality is especially necessary in embedded or remote systems where manually resetting the system isn’t practical or even possible.

How Can I Implement a Watchdog Timer in My Embedded System?

There are two primary methods for implementing watchdog timers:

  • Using a processor with integrated watchdog functionality. Many microcontrollers such as the MSP430F5529 series have integrated watchdog functionality. This is valuable because it is very easy to implement and no other ICs are required. However, it comes with one major caveat: integrated watchdogs may not always work as desired because the code issues that cause the MCU to malfunction could also inadvertently disable the watchdog timer. Again, software is written in such a way that an internal watchdog should be able to detect any freezes or hangs. However, taking the extra steps to monitor the watchdog input in a redundant manner can help account for unforeseen errors in code.
  • Using a voltage supervisor with a watchdog timer. A supervisor with watchdog-timer functionality such as the TPS3851 or the TPS3110 allows you monitor both the supply voltage and watchdog signal in an external, redundant fashion. Should the internal watchdog of the processor fail to detect an errant or missing pulse, the external watchdog timer will add a level of detection not achievable otherwise.

In principle, the functionality of a watchdog timer is not overly complicated. However, its importance in maintaining the reliability of systems cannot be overstated. This is especially true if a human-initiated system reset in case of failure is not possible or very difficult.

Additional Resources