SPRZ422K August   2014  – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
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      16.      Advisory
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      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
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      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
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      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
      37.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

ADC: Random Conversion Errors

Revisions Affected

B

Details

The ADC may have errors at a rate as high as 1 in 106.5 ADC conversions in 12-bit mode and as high as 1 in 108.75 conversions in 16-bit mode. When a conversion error occurs, it will be a significant random jump in the digital output of the ADC without a corresponding change in the ADC input voltage, otherwise known as a “sparkle code”. The magnitude of this jump will typically be in the range of 20 LSBs to 200 LSBs; however, larger or smaller jumps may occur.

Workarounds

For the revisions affected, the error rate will be lower than 1 error in 1014.5 ADC conversions for both 12-bit mode and 16-bit mode when all of the following configurations are used:

  • The S+H duration is at least 320 ns
  • ADCCLK is 40 MHz or less
  • ADCCLK prescale is a whole number: /1.0, /2.0, /3.0, /4.0, /5.0, /6.0, /7.0, or /8.0
  • The value of 0x7000 is written to memory locations 0x0000 743F, 0x0000 74BF, 0x0000 753F, and 0x0000 75BF (writing this value is only valid when the ADCCLK prescale is a whole number).