SPRUJ81 February   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Width/Spacing Proposal for Escapes
  4. 3 Stackup
  5. 4 Via Sharing
  6. 5 Floorplan Component Placement
  7. 6 Critical Interfaces Impact Placement
  8. 7 Routing Priority
  9. 8 SerDes Interfaces
  10. 9 DDR Interfaces
  11. 10Power Decoupling
  12. 11Route Lowest Priority Interfaces Last
  13. 12Summary

1 Introduction

The AM62Ax is based on the Cortex-A53 microprocessor, M4F microcontroller with dedicated peripherals, 3D graphics acceleration, dual display interfaces, and extensive peripheral and networking options for a variety of embedded applications. The AM62Ax is available in a 18-mm ˟ 18-mm FBGA package with a 0.8-mm ball pitch. The package BGA design is built leveraging TI Flip Chip BGA Technology (FC-BGA) technology. This document is intended to provide a reference for escape routing on the AM62Ax device. Care must be taken to route signals with special requirements such as DDR, high speed interfaces. Refer to the High-Speed Interface Layout Guidelines and DDR Routing Guidelines for more details. Details on Power Delivery Network are provided in AM62x PDN Application note and any routing and layout requirements specified in those documents supersede the generic requirements provided here.