SPRUIX1B October 2022 – April 2024 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137
Table 3-84 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-84 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
8h | PARTIDL | Lower 32-bit of Device PART Identification Number | Go | |
Ah | PARTIDH | Upper 32-bit of Device PART Identification Number | Go | |
Ch | REVID | Device Revision Number | Go | |
74h | TRIMERRSTS | TRIM Error Status register | Go | |
86h | SOFTPRES2 | EPWM Software Reset register | EALLOW | Go |
88h | SOFTPRES3 | ECAP Software Reset register | EALLOW | Go |
8Ah | SOFTPRES4 | EQEP Software Reset register | EALLOW | Go |
90h | SOFTPRES7 | SCI Software Reset register | EALLOW | Go |
92h | SOFTPRES8 | SPI Software Reset register | EALLOW | Go |
94h | SOFTPRES9 | I2C Software Reset register | EALLOW | Go |
96h | SOFTPRES10 | CAN Software Reset register | EALLOW | Go |
9Ch | SOFTPRES13 | ADC Software Reset register | EALLOW | Go |
9Eh | SOFTPRES14 | CMPSS Software Reset register | EALLOW | Go |
ACh | SOFTPRES21 | DCC Software Reset register | EALLOW | Go |
B8h | SOFTPRES27 | EPG Software Reset register | EALLOW | Go |
BAh | SOFTPRES28 | Flash Software Reset register | EALLOW | Go |
130h | TAP_STATUS | Status of JTAG State machine & Debugger Connect | Go | |
19Bh | ECAPTYPE | Configures ECAP Type for the device | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-85 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
PARTIDL is shown in Figure 3-74 and described in Table 3-86.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INSTASPIN | RESERVED | RESERVED | PIN_COUNT | |||
R-0h | R-X | R-0h | R-X | R-X | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUAL | RESERVED | RESERVED | RESERVED | ||||
R-X | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | RESERVED | R | 0h | Reserved |
23-16 | RESERVED | R | X | Reserved |
15 | RESERVED | R | 0h | Reserved |
14-13 | INSTASPIN | R | X | 1 = InstaSPIN-FOC 2 = NONE 3 = NONE Reset type: PORESETn |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | X | Reserved |
10-8 | PIN_COUNT | R | X | 0 = 56 pin QFN 1 = 64 pin (QFP - Q100) 2 = 64 pin (QFP) 3 = 80 pin (QFP) 4 = 48 pin (QFP) 5 = 32 pin (QFN) 6 = Reserved 7 = 48 pin (QFN) 8 = 64 pin (QFP) - VREGENZ bondout Reset type: PORESETn |
7-6 | QUAL | R | X | 0 = Engineering sample (TMX) 1 = Pilot production (TMP) 2 = Fully qualified (TMS) Reset type: PORESETn |
5 | RESERVED | R | 0h | Reserved |
4-3 | RESERVED | R | 0h | Reserved |
2-0 | RESERVED | R | 0h | Reserved |
PARTIDH is shown in Figure 3-75 and described in Table 3-87.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEVICE_CLASS_ID | PARTNO | ||||||||||||||
R-6h | R-X | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAMILY | RESERVED | RESERVED | |||||||||||||
R-5h | R-0h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DEVICE_CLASS_ID | R | 6h | Device class ID Reset type: PORESETn |
23-16 | PARTNO | R | X | Refer to Datasheet for Device Part Number Reset type: PORESETn |
15-8 | FAMILY | R | 5h | Device Family Reset type: PORESETn |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | RESERVED | R | 0h | Reserved |
REVID is shown in Figure 3-76 and described in Table 3-88.
Return to the Summary Table.
Device Revision Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REVID | ||||||||||||||||||||||||||||||
R-0-0h | R/WOnce-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | REVID | R/WOnce | 0h | Device Revision ID. Loaded from flash trim sector by boot rom. Reset value is die-specific. Reset type: XRSn |
TRIMERRSTS is shown in Figure 3-77 and described in Table 3-89.
Return to the Summary Table.
TRIM Error Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LERR | ||||||||||||||||||||||||||||||
R-0-0h | R/WSonce-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | LERR | R/WSonce | 0h | TRIM information load error status. This will include error during SRAM repair also. 0x1: Correctable single bit error 0x2: Uncorrectable double bit error 0x20: Trim over timeout error Other: Non zero value indicates error during load Note: [1] This bit is updated by software. Details will be filled in once the Boot ROM related requirements are complete. It should have bits to indicate (i) Double bit error during trim load (ii) Single bit error during trim load (iii) Double bit error during SRAM repair load (iv) Single bit error error during SRAM repair load (v) SRAM repair error load (chain is broken) (vi) PWRUPSTS.TRIMOVER signal is not asserted even after the full wait time Reset type: XRSn |
SOFTPRES2 is shown in Figure 3-78 and described in Table 3-90.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | EPWM7 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
5 | EPWM6 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
4 | EPWM5 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
3 | EPWM4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | EPWM3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | EPWM2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | EPWM1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES3 is shown in Figure 3-79 and described in Table 3-91.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ECAP2 | ECAP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | ECAP2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | ECAP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES4 is shown in Figure 3-80 and described in Table 3-92.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | EQEP1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | EQEP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES7 is shown in Figure 3-81 and described in Table 3-93.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SCI_C | SCI_B | SCI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | SCI_C | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | SCI_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SCI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES8 is shown in Figure 3-82 and described in Table 3-94.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | SPI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | SPI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES9 is shown in Figure 3-83 and described in Table 3-95.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I2C_B | I2C_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | I2C_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | I2C_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES10 is shown in Figure 3-84 and described in Table 3-96.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | CAN_A |
R-X | R-X | R-X | R-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | RESERVED | R | X | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | CAN_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES13 is shown in Figure 3-85 and described in Table 3-97.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ADC_C | RESERVED | ADC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | ADC_C | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | ADC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES14 is shown in Figure 3-86 and described in Table 3-98.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMPSS4 | CMPSS3 | CMPSS2 | CMPSS1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMPSS4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | CMPSS3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | CMPSS2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | CMPSS1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES21 is shown in Figure 3-87 and described in Table 3-99.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | DCC0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | DCC0 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES27 is shown in Figure 3-88 and described in Table 3-100.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPG1 | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | EPG1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES28 is shown in Figure 3-89 and described in Table 3-101.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLASHA | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | FLASHA | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Note: Whenever the reset to flash is asserted, it will be internally stretched to ~15us Reset type: SYSRSn |
TAP_STATUS is shown in Figure 3-90 and described in Table 3-102.
Return to the Summary Table.
Status of JTAG State machine & Debugger Connect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DCON | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TAP_STATE | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAP_STATE | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DCON | R | 0h | DebugConnect indication from IcePick. Reset type: PORESETn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | TAP_STATE | R | 0h | TAP State Vector. With bits representing, Connect coresponding POTAP* output to the 0:TLR, 1:IDLE, 2:SELECTDR, 3:CAPDR, 4:SHIFTDR, 5:EXIT1DR, 6:PAUSEDR, 7:EXIT2DR, 8:UPDTDR, 9:SLECTIR, 10:CAPIR, 11:SHIFTIR, 12:EXIT1IR, 13:PAUSEIR, 14:EXIT2IR, 15:UPDTIR, Reset type: PORESETn |
ECAPTYPE is shown in Figure 3-91 and described in Table 3-103.
Return to the Summary Table.
Based on the configuration enables disables features associated with the ECAP type.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | RESERVED | ||||||
R/WSonce-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TYPE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R/WSonce | 0h | 1: Write to this register is not allowed. 0: Write to this register is allowed. Reset type: SYSRSn |
14-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | TYPE | R/W | 0h | '00,10,11' : 1. No EALLOW protection to ECAP registers. '01' : 1. ECAP registers are EALLOW protected. Reset type: SYSRSn |