SPRUIW3 October 2021 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
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F28003x is both a subset and superset of F28004x. They have two packages in common, 64-pin and 100-pin. It is possible to migrate between F28003x and F28004x with the caveats in this document taken into account.
An overlaid block diagram of F28004x and F28003x is shown in Figure 1-1 while feature comparison of the superset part numbers for the F28003x and F28004x devices is shown in Table 1-1.
Feature | F28004x | F28003x | ||||||
---|---|---|---|---|---|---|---|---|
100-Pin PZ | 64-Pin PM | 56-Pin RSH | 100-Pin PZ | 80-Pin PN | 64-Pin PM | 48-Pin PT | ||
Processor and Accelerators | ||||||||
C28x | Frequency (MHz) | 100 | 120 | |||||
FPU | Yes | Yes (instructions for Fast Integer Division) | ||||||
VCU–I | Yes | – | ||||||
VCRC | – | Yes | ||||||
TMU | Yes – Type 0 | Yes – Type 1 (instructions supporting NLPID) | ||||||
CLA – Type 2 | Available | Yes | ||||||
Frequency (MHz) | 100 | 120 | ||||||
6–Channel DMA – Type 0 | Yes | |||||||
External interrupts | 5 | |||||||
Memory | ||||||||
Flash | 256KB (128Kw) | 384KB (192Kw) | ||||||
RAM | Dedicated | 4KB (2Kw) | ||||||
Local Shared | 32KB (16Kw) | |||||||
Message | 0.5KB (0.25Kw) | 1KB (0.5Kw) | ||||||
Global Shared | 64KB (32Kw) | 32KB (16Kw) | ||||||
Total | 100.5KB (50.25Kw) | 69KB (34.5Kw) | ||||||
Message RAM Types | 512B (256w) CPU–CLA | 512B (256w) CPU–CLA 512B (256w) CLA–DMA | ||||||
ECC | FLASH, Mx | FLASH, Mx, LSx, GSx, Message RAM | ||||||
Parity | LSx, GSx, Message RAM, CAN RAM | ROM, CAN RAM | ||||||
Code security for on–chip flash and RAM | Yes | |||||||
System | ||||||||
Configurable Logic Block (CLB) | 4 Tiles – Type 2 | 4 Tiles – Type 3 | ||||||
Embedded Pattern Generator (EPG) | - | Yes | ||||||
Motor Control Libraries in ROM | Yes | |||||||
32–bit CPU timers | 3 | |||||||
Advance Encryption Standard (AES) | – | Yes | ||||||
Background CRC (BGCRC) | – | Yes | ||||||
Live Firmware Update (LFU) Support | Yes | Yes, with enhancements and flash bank erase time improvements | ||||||
Secure Boot | – | Yes | ||||||
JTAG Lock | – | Yes | ||||||
HWBIST | – | Yes | ||||||
Nonmaskable Interrupt Watchdog (NMIWD) timers | 1 | |||||||
Watchdog timers | 1 | |||||||
Crystal oscillator/External clock input | 1 | |||||||
Internal oscillator | 2 | |||||||
Pins and Power Supply | ||||||||
Internal 3.3v to 1.2v Voltage Regulator | VREG LDO | Yes | ||||||
DCDC | Yes | – | ||||||
GPIO pins | 35 | 21 | 20 | 51 | 39 | 26 | 14 | |
Additional GPIO | 5 (2 from cJTAG, 1 from X2 and 2 from DCDC) | 4 (2 from cJTAG and 2 from X1/X2) | ||||||
AIO (analog with digital inputs) | 21 | 14 | 12 | 23 | 16 | 16 | 14 | |
AGPIO (analog with digital inputs and outputs) | - | 2 | 2 | - | - | |||
Analog Peripherals | ||||||||
ADC 12–bit | Number of ADCs | 3 | ||||||
MSPS | 3.45 | 4 | ||||||
Conversion Time (ns) | 290 | 250 | ||||||
ADC channels (single–ended) - includes the two gpdac outputs | 21 | 14 | 12 | 23 | 18 | 16 | 14 | |
Temperature sensor | 1 | |||||||
Buffered DAC | 2 | |||||||
CMPSS (each CMPSS has two comparators and two internal DACs) | 7 | 6 | 5 | 4 | ||||
PGA (Gain Settings: 3, 6, 12, 24) | 7 | 5 | 4 | – | ||||
Control Peripherals | ||||||||
eCAP/HRCAP modules | 7 (2 with HRCAP capability) – Type 1 | 3 (1 with HRCAP capability) – Type 2 | ||||||
ePWM/HRPWM channels – Type 4 | 16 (16 with HRPWM) | 16 (8 with HRPWM) | ||||||
eQEP modules | 2 – Type 1 | 1 – Type 1 | 2 – Type 2 | |||||
SDFM channels | 4 – Type 1 | 3 – Type 1 | 8 – Type 2 | |||||
Communication Peripherals | ||||||||
CAN (DCAN) – Type 0 | 2 | 1 | ||||||
CANFD (MCAN) – Type 2 | – | 1 | ||||||
FSI | 1 (1 RX and 1 TX) – Type 0 | 1 (1 RX and 1 TX) – Type 2 | ||||||
I2C – Type 1 | 1 | 2 | ||||||
LIN – Type 1 | 1 | 2 | ||||||
HIC - Type 1 | No | Yes | ||||||
PMBus – Type 0 | 1 | |||||||
SCI – Type 0 | 2 | |||||||
SPI – Type 2 | 2 | |||||||
Package Options, Temperature, and Qualification | ||||||||
Junction temperature (TJ) | –40°C to 125°C | –40°C to 150°C | ||||||
Free-Air temperature (TA) | –40°C to 125°C | |||||||
Package Options with AEC-Q100 Qualification available | Yes | Yes | – | Yes | – | Yes | Yes |
The F28004x and F28003x devices have two packages in common: 100-Pin PZ and 64-Pin PM. There are two kinds of migration that can happen between the two devices:
For the second migration type above, the dual-routing technique maximizes pin utilization. The following sections describe the pin migration in detail.
This section describes the F28003x and F28004x differences that exist between the 100-Pin PZ package. The Q and non-Q variant of the 100-Pin PZ package have the same pinout per device. Figure 2-1 outlines the differences.
If the PCB is already designed and you are moving from F28004x/F28003x to F28003x/F28004x respectively, dual routing is not possible and hence those pins become incompatible between the two devices, Table 2-1 outlines the migration.
For the color legend, see Figure 2-1.
Pin No | Pin Name | Transition Type | Action | ||
---|---|---|---|---|---|
F28004x | F28003x | F28003x to F28004x | F28004x to F28003x | ||
Minor Incompatibility - Signals in Common (1) | |||||
28 | PGA6_IN, C5 | C5, A12 | Common Analog Channel | Use C5 | |
31 | PGA4_IN, C3 | C3, A7 | Use C3 | ||
36 | A4, B8, PGA2_OF | A4, B8 | Use A4 or B8 | ||
37 | A8, PGA6_OF | A8 | Use A8 | ||
39 | B4, C8, PGA4_OF | B4, C8 | Use B4 or C8 | ||
40 | A10, B1, C10, PGA7_OF | A10, B1, C10 | Use A10, B1 or C10 | ||
21 | C2 | C2, B12 | Use C2 | ||
22 | A1, DACB_OUT | A1, DACB_OUT, B7 | Use A1 or DACB_OUT | ||
41 | B0 | B0, C11 | Use B0 | ||
69 | X1 | GPIO19, X1 | Common Clock | GPIO19 not available for use | |
81 | GPIO23_VSW | GPIO23 | Common GPIO | Do not use DCDC. GPIO22 & GPIO23 available for use | |
83 | GPIO22_VFBSW | GPIO22 | |||
Medium Incompatibility - Different Signals, Same Type | |||||
17 | C4 | A2, B6, C9 | Analog Function Compatible | Update code to C4 | Update code to A2, B6 or C9 |
19 | C0 | A14, B14, C4 | Update code to C0 | Update code to A14, B14 or C4 | |
85 | GPIO40 | GPIO44 | GPIO Function Compatible | Update code to GPIO40 | Update code to GPIO44 |
91 | GPIO39 | GPIO61 | Update code to GPIO39 | Update code to GPIO61 | |
Major Incompatibility - Different Signals and Types | |||||
14 | PGA1_GND | A6 | PGA Ground to ADC Channel | Do not use, follow the guidelines for unused pins in the datasheet as applicable | |
15 | PGA3_GND | B2, C6 | |||
32 | PGA6_GND, PGA2_GND, PGA4_GND | B5 | |||
42 | PGA7_GND | C14 | |||
13 | PGA5_GND | GPIO54 | PGA Ground to GPIO | ||
12 | VSSA | GPIO53 | Ground to GPIO | ||
82 | VSS_SW | GPIO41 | |||
11 | VDDA | GPIO52 | Power to GPIO | ||
80 | VDDIO_SW | GPIO40 | |||
16 | PGA5_IN | B3, VDAC | PGA Input to ADC Channel | ||
18 | PGA1_IN | C7, B9, A3 | |||
20 | PGA3_IN | A11, B10, C0 | |||
30 | PGA2_IN | B11 | |||
43 | PGA7_IN | GPIO55 | PGA Input to GPIO | ||
6 | A6, PGA5_OF | GPIO47 | Analog to GPIO | ||
7 | B2, C6, PGA3_OF | GPIO48 | |||
8 | B3, VDAC | GPIO49 | |||
9 | A2, B6, PGA1_OF | GPIO50 | |||
10 | A3 | GPIO51 | |||
44 | C14 | GPIO60 | |||
48 | FLT2 | GPIO20, B5 | Flash Test Pins to GPIO/Analog | ||
49 | FLT1 | GPIO21, B11 |
If the PCB is yet to be designed and you are moving from F28004x/F28003x to F28003x/F28004x, respectively, the dual routing technique illustrated in Figure 2-2 maximizes pin utilization. The complete pin migration is outlined in Table 2-2.
For the color legend, see Figure 2-1.
Pin No | Pin Name | Transition Type | Action | ||
---|---|---|---|---|---|
F28004x | F28003x | F28003x to F28004x | F28004x to F28003x | ||
Minor Incompatibility - Signals in Common (1) | |||||
28 | PGA6_IN, C5 | C5, A12 | Common Analog Channel | Use C5 | |
31 | PGA4_IN, C3 | C3, A7 | Use C3 | ||
36 | A4, B8, PGA2_OF | A4, B8 | Use A4 or B8 | ||
37 | A8, PGA6_OF | A8 | Use A8 | ||
39 | B4, C8, PGA4_OF | B4, C8 | Use B4 or C8 | ||
40 | A10, B1, C10, PGA7_OF | A10, B1, C10 | Use A10, B1 or C10 | ||
21 | C2 | C2, B12 | Use C2 | ||
22 | A1, DACB_OUT | A1, DACB_OUT, B7 | Use A1 or DACB_OUT | ||
41 | B0 | B0, C11 | Use B0 | ||
69 | X1 | GPIO19, X1 | Common Clock | GPIO19 not available for use | |
81 | GPIO23_VSW | GPIO23 | Common GPIO | Do not use DCDC. GPIO22 & GPIO23 available for use | |
83 | GPIO22_VFBSW | GPIO22 | |||
Medium Incompatibility - Different Signals, Same Type | |||||
19 | C0 | A14, B14, C4 | Analog Function Compatible | Update code to C0 | Update code to A14, B14 or C4 |
85 | GPIO40 | GPIO44 | GPIO Function Compatible | Update code to GPIO40 | Update code to GPIO44 |
91 | GPIO39 | GPIO61 | Update code to GPIO39 | Update code to GPIO61 | |
Medium Incompatibility - Dual Routing | |||||
6 | A6, PGA5_OF | GPIO47 | Dual PCB Route, F28004x 0-Ohm Resistor, F28003x DNP | Dual route to Pin 6 & 14 | |
7 | B2, C6, PGA3_OF | GPIO48 | Dual route to Pin 7 & 15 | ||
8 | B3, VDAC | GPIO49 | Dual route to Pin 8 & 16 | ||
9 | A2, B6, PGA1_OF | GPIO50 | Dual route to Pin 9 & 17 | ||
10 | A3 | GPIO51 | Dual route to Pin 10 & 18 | ||
14 | PGA1_GND | A6 | Dual PCB Route, F28004x DNP, F28003x 0-Ohm Resistor | Dual route to Pin 6 & 14 | |
15 | PGA3_GND | B2, C6 | Dual route to Pin 7 & 15 | ||
16 | PGA5_IN | B3, VDAC | Dual route to Pin 8 & 16 | ||
17 | C4 | A2, B6, C9 | Dual route to Pin 9 & 17 | ||
18 | PGA1_IN | C7, B9, A3 | Dual route to Pin 10 & 18 | ||
Major Incompatibility - Different Signals and Types | |||||
32 | PGA6_GND, PGA2_GND, PGA4_GND | B5 | PGA Ground to ADC Channel | Tie to VSS | |
42 | PGA7_GND | C14 | |||
13 | PGA5_GND | GPIO54 | PGA Ground to GPIO | Tie to VSS through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIOs | |
12 | VSSA | GPIO53 | Ground to GPIO | ||
82 | VSS_SW | GPIO41 | |||
11 | VDDA | GPIO52 | Power to GPIO | Tie to VDDIO through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIOs | |
80 | VDDIO_SW | GPIO40 | |||
20 | PGA3_IN | A11, B10, C0 | PGA Input to ADC Channel | No connect. Enable internal pull-up for the GPIOs on F28003x | |
30 | PGA2_IN | B11 | |||
43 | PGA7_IN | GPIO55 | PGA Input to GPIO | ||
44 | C14 | GPIO60 | Analog to GPIO | ||
48 | FLT2 | GPIO20, B5 | Flash Test Pins to GPIO | ||
49 | FLT1 | GPIO21, B11 |
This section describes the F28003x and F28004x differences that exist between the Q and non-Q variants of the 64-Pin PM package. Figure 2-3 shows the differences for the non-Q variant and Figure 2-4 shows the differences for the Q variant.
Table 2-3 outlines the migration moving from F28004x/F28003x to F28003x/F28004x, respectively.
For the color legend, see Figure 2-3 and Figure 2-4.
Pin No | Pin Name | Transition Type | Action | ||
---|---|---|---|---|---|
F28004x | F28003x | F28003x to F28004x | F28004x to F28003x | ||
Minor Incompatibility - Signals in Common (1) | |||||
6 | A6, PGA5_OF | A6 | Common Analog Channel | Use A6 | |
7 | B2, C6, PGA3_OF | B2, C6 | Use B2 or C6 | ||
8 | B3, VDAC | A3, B3, C5 VDAC | Use B3 or VDAC | ||
9 | A2, B6, PGA1_OF | A2, B6, C9 | Use A2 or B6 | ||
11 | PGA5_IN, C4 | A14, B14, C4 | Use C4 | ||
12 | PGA1_IN, C0 | A11, B10, C0 | Use C0 | ||
13 | PGA3_IN, C2 | A5, B12, C2 | Use C2 | ||
14 | A1, DACB_OUT | A1, B7, DACB_OUT | Use A1 or DACB_OUT | ||
18 | C1 | A12, C1 | Use C1 | ||
19 | PGA4_IN, C3 | A7, C3 | Use C3 | ||
23 | C14 | A4, B8, C14 | Use C14 | ||
24 | B4, C8 | A9, B4, C8 | Use B4 or C8 | ||
42 | X1 | GPIO19, X1 | Common Clock | GPIO19 not available for use | |
54 | GPIO23_VSW | GPIO23 | Common GPIO | Do not use DCDC. GPIO22 & GPIO23 available for use | |
56 | GPIO22_VFBSW | GPIO22 | |||
Major Incompatibility - Different Signals and Types | |||||
10 | PGA1_GND, PGA3_GND, PGA5_GND | A15, B9, C7 | PGA Ground to ADC Channel | Tie to VSS | |
20 | PGA2_GND, PGA4_GND, PGA6_GND | A8, B0, C11 | |||
55 | VSS_SW | GPIO41 | Ground to GPIO | Tie to VSS through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO | |
53 | VDDIO_SW | GPIO40 | Power to GPIO | Tie to VDDIO through 0-Ohm resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO | |
(Non-Q Variant) Major Incompatibility - Different Signals and Types | |||||
46 | VREGENZ | GPIO39 | External VREG not supported. Tie to VSS through 0-Ω resistor. Depopulate resistor when using F28003x and enable internal pull-up for the GPIO | ||
(Q Variant) Major Incompatibility - Different Signals and Types | |||||
29 | FLT2 | GPIO13 | Flash Test Pins to GPIO | No connect. Enable internal pull-up for the GPIOs on F28003x | |
30 | FLT1 | GPIO12 |
The differences and similarities that exist when moving between the F28003x and F28004x devices is explored in this section.
This section outlines features that only exist in the F28003x device. For details on each of these new features, see the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual (SPRUIW9).
Two instructions have been added to the instruction set of the Trigonometrical Math Unit (TMU) on F28003x to support computation of the floating-point power function “powf”. These instructions calculate the inverse binary exponent in base two logarithm and can be combined to compute the power of a floating-point number raised to the power of another floating-point number.
This calculation would typically take 300 cycles using library emulation, but takes less than ten cycles using the new instructions. An example of the application of the power function is non-linear proportional integral derivative control (NLPID), which is a component of the C2000 Digital Control Library found in C2000Ware.
The C28x processor Fast Integer Division (FINTDIV) unit provides an open and scalable approach to facilitate different data type sizes (16/16, 32/16, 32/32, 64/32, 64/64), signed and unsigned or mixed data type versions (ui32/ui32, i32/ui32, i32/i32) and for additional performance, the operations return both the integer and remainder portion of the calculation simultaneously.
The division operations are interruptible so as to enable minimum latency for higher priority tasks, a critical requirement for high performance real-time control applications. Unique to this fast integer division unit is support for Truncated, Modulo and Euclidean division formats without any cycle penalty. Each of these formats represents the integer and remainder result in different forms. Below is a brief summary of the various division formats:
Both the Euclidean and Modulo formats are more appropriate for precise control applications because the integer value is linear around the zero point and, hence, avoid potential calculation hysteresis. The C28x compiler supports all three division formats for all data types.
The Host Interface Controller (HIC) is a new module for the F28003x device that allows an external host controller to directly access resources of the F28003x device using the ASRAM protocol. HIC was first introduced in F28002x.
The Background CRC (BGCRC) is a new module for the F28003x device that can compute the CRC-32 value of a configurable block of memory. It is an upgrade on the CLAPROMCRC found in the F28004x device to test more memories than just the CLA ROM. BGCRC was first introduced in F2838x.