SPRUIF3B May   2017  – March 2019 DRA790 , DRA791 , DRA793 , DRA797

 

  1.   DRA79x EVM CPU board
    1.     Trademarks
    2. 1 Introduction
    3. 2 Overview
      1. 2.1 EVM System Configurations
      2. 2.2 CPU Board Feature List
      3. 2.3 CPU Board Component Identification
    4. 3 Hardware
      1. 3.1 Hardware Architecture
      2. 3.2 DRA71x, DRA79x, TDA2E-17, and AM570x Processor
      3. 3.3 Power Architecture
      4. 3.4 Reset Structure
      5. 3.5 Clocks
      6. 3.6 Memory
        1. 3.6.1  SDRAM Memory
        2. 3.6.2  QSPI Flash Memory
        3. 3.6.3  EMMC Flash Memory
        4. 3.6.4  MicroSD Card Cage
        5. 3.6.5  GPMC NOR Flash Memory
        6. 3.6.6  GPMC NAND Flash Memory
        7. 3.6.7  Boot Modes
        8. 3.6.8  JTAG/Emulator and Trace
        9. 3.6.9  UART Terminal
        10. 3.6.10 DCAN and CAN Interfaces
        11. 3.6.11 Universal Serial Bus (USB)
        12. 3.6.12 Wired Ethernet
        13. 3.6.13 Video Output
          1. 3.6.13.1 HDMI Display
          2. 3.6.13.2 LCD Touch Panel
          3. 3.6.13.3 FPD-Link III Output/Panel
        14. 3.6.14 Video Input
          1. 3.6.14.1 Parallel Imaging
          2. 3.6.14.2 Serial Imaging
        15. 3.6.15 Mini-PCIe
        16. 3.6.16 Media Local Bus (MLB)
        17. 3.6.17 Audio
        18. 3.6.18 COM8 Module Interface
        19. 3.6.19 eFuse Programming Supply
        20. 3.6.20 User Interface LEDs
        21. 3.6.21 Power Monitoring
        22. 3.6.22 I2C Peripheral Map
        23. 3.6.23 GPIO List
        24. 3.6.24 I/O Expander List
        25. 3.6.25 Configuration EEPROM
    5. 4 Signal Multiplex Logic
      1. 4.1 GPMC and QSPI Selection (MUX A)
      2. 4.2 GPMC, VIN1, and VOUT3 Selection (MUX B)
      3. 4.3 GPMC and EMMC Selection (MUX C)
      4. 4.4 VIN2A and EMU Selection (MUX D, MUX E)
      5. 4.5 VIN2A and RGMII1 Selection (MUX F)
      6. 4.6 RGMII0 and VIN1B Selection (MUX J)
      7. 4.7 SPI2 and UART3 Selection (MUX K)
      8. 4.8 DCAN2 and I2C3 Selection (MUX L)
    6. 5 USB3 Supported Configurations
      1. 5.1 Option 1
      2. 5.2 Option 2
      3. 5.3 Option 3
    7. 6 References
  2.   Revision History

4 Signal Multiplex Logic

Due to the high level of multiplexing on the SoC (over 16 levels), multiplex control logic is required to use different signals on the same SoC pins with their various functionality. The following information provides description of the logic.

An I2C-based I/O expander controls the onboard MUXs. Table 14 lists the specific bits assigned to each MUX, as well as the specific settings for the various selections.

Table 14. Onboard MUX Setting and Control

MUX Control Bits Value MUX Setting
A NA NA QSPI Memory (default)
NA NOR Memory (requires resistor change)
C
(RU4)		 SW8.3 Off NOR Memory
On EMMC Memory
EXP3.P[15:14] 00 EMMC Memory
01 Memory selected by SW8.3
10 NOR Memory
11 Memory selected by SW8.3 (default)
B
(RU9, RU11, RU24)		 EXP2.P[7,0] 00 Reserved
01 VIN1A to Expansion
10 VOUT3 to LCD Panel
11 GPMC NOR/NAND (default)
D
(RU6)		 EXP3.P[6,2] 00 Reserved
01 Peripheral selected by MUX E (desired default)
10 VIN2A to Expansion
11 Open (default)
E
(RU12, RU23)		 EXP2.P[17,14] 00 Reserved
01 VOUT2 to FPD-Link III Transmitter
10 VIN2A to LI Camera
11 EMU (default)
F
(RU27)		 EXP3.P[12,11] 00 Reserved
01 Peripheral selected by MUX E
10 VIN2A to Expansion
11 RGMII1 to Ethernet Port 1 (default)
K
(RJ12)		 EXP2.P16 0 UART3 to COM8Q
1 Route to Expansion (SPI2) (default)
L
(RU18)		 EXP2.P3 0 Route to Expansion (I2C3)
1 Route to DCAN2 Connector (default)
J
(RU25)		 EXP2.P4 0 Route to Expansion (VIN1B)
1 RGMII0 to Ethernet Port 0 (default)
M
(RU8)		 EXP3.P13 0 Route to Expansion (VIN2B)
1 Route to Expansion (MMC3/legacy) (default)
G
(RU26)		 SW8.7 Off Use Default NOR Address (default)
On Use Alternate NOR Address (with EMMC)
H
(RU10)		 EXP3.P1 0 Route to COM8Q (MASP3/7)
1 Route to Expansion (McASP3/7) (default)