SPRACY7 October   2021 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Supplementary Information
  3. 2Clock Generator
    1. 2.1 Generating Two Offset Clocks
  4. 3Signal Generator
    1. 3.1 Two Offset Clocks Generated by the SIGGEN0 Module
    2. 3.2 Generate Serial Data With Rotate Mode
      1. 3.2.1 Rotate Right Once - CPOL = 0, CPHA = 1
      2. 3.2.2 Rotate Right Once - CPOL=0, CPHA=0
      3. 3.2.3 Rotate Right Once - CPOL=1, CPHA=1
      4. 3.2.4 Rotate Right Once - CPOL=1, CPHA=0
      5. 3.2.5 Shift Right Once - CPOL=1, CPHA=0
      6. 3.2.6 Shift Right Once - CPOL=0, CPHA=0
  5. 4Summary
  6. 5References

3.2.2 Rotate Right Once - CPOL=0, CPHA=0

In order to generate the same data on the SPI data line as the previous example , this time with CPOL=0 and CPHA=0 mode signal format, the EPG SIGGEN DATA bit stream must be updated.

The clock and data bit stream for CPOL=0 and CPHA=0 is shown below.

//
// Data
//
#define SIG_GEN_DATA0_0_15    0b1110000110011111U

//
// Clock - Data latched on falling edge, during idle CLK is LOW
//
#define SIG_GEN_DATA0_16_31   0b1010101010101010U

In this mode, falling edges latch the data, and the data line must be delayed.

Note: the SIG_GEN_DATA0_0_15 in this example, is the same as the SIG_GEN_DATA0_0_15 last example but rotated left by 1.
Note: This SPI CLK and DATA mode can be generated through the SHIFT RIGHT ONCE mode without the need for the SIG_GEN_DATA0_0_15 from the previous example to be rotated left.

Figure 3-9 EPG SIGGEN Bit Stream for SPI CLK and DATA (CPOL=0, CPHA=0)
Figure 3-10 Rotate Right Once - CPOL=0, CPHA=0