SPNS242A October   2014  – June 2015

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Terminal Functions
      1. 4.2.1  High-End Timer (N2HET)
      2. 4.2.2  Enhanced Quadrature Encoder Pulse Modules (eQEP)
      3. 4.2.3  General-Purpose Input/Output (GPIO)
      4. 4.2.4  Controller Area Network Interface Modules (DCAN1, DCAN2)
      5. 4.2.5  Multibuffered Serial Peripheral Interface (MibSPI1)
      6. 4.2.6  Standard Serial Peripheral Interface (SPI2)
      7. 4.2.7  Local Interconnect Network Controller (LIN)
      8. 4.2.8  Multibuffered Analog-to-Digital Converter (MibADC)
      9. 4.2.9  System Module
      10. 4.2.10 Error Signaling Module (ESM)
      11. 4.2.11 Main Oscillator
      12. 4.2.12 Test/Debug Interface
      13. 4.2.13 Flash
      14. 4.2.14 Core Supply
      15. 4.2.15 I/O Supply
      16. 4.2.16 Core and I/O Supply Ground Reference
    3. 4.3 Output Multiplexing and Control
      1. 4.3.1 Notes on Output Multiplexing
      2. 4.3.2 General Rules for Multiplexing Control Registers
    4. 4.4 Special Multiplexed Options
      1. 4.4.1 Filtering for eQEP Inputs
        1. 4.4.1.1 eQEPA Input
        2. 4.4.1.2 eQEPB Input
        3. 4.4.1.3 eQEPI Input
        4. 4.4.1.4 eQEPS Input
      2. 4.4.2 N2HET PIN_nDISABLE Input Port
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Thermal Resistance Characteristics for PZ
    9. 5.9  Input/Output Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
  6. 6System Information and Electrical Specifications
    1. 6.1  Voltage Monitor Characteristics
      1. 6.1.1 Important Considerations
      2. 6.1.2 Voltage Monitor Operation
      3. 6.1.3 Supply Filtering
    2. 6.2  Power Sequencing and Power-On Reset
      1. 6.2.1 Power-Up Sequence
      2. 6.2.2 Power-Down Sequence
      3. 6.2.3 Power-On Reset: nPORRST
        1. 6.2.3.1 nPORRST Electrical and Timing Requirements
    3. 6.3  Warm Reset (nRST)
      1. 6.3.1 Causes of Warm Reset
      2. 6.3.2 nRST Timing Requirements
    4. 6.4  ARM Cortex-R4 CPU Information
      1. 6.4.1 Summary of ARM Cortex-R4 CPU Features
      2. 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software
      3. 6.4.3 Dual Core Implementation
      4. 6.4.4 Duplicate clock tree after GCLK
      5. 6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety
      6. 6.4.6 CPU Self-Test
        1. 6.4.6.1 Application Sequence for CPU Self-Test
        2. 6.4.6.2 CPU Self-Test Clock Configuration
        3. 6.4.6.3 CPU Self-Test Coverage
    5. 6.5  Clocks
      1. 6.5.1 Clock Sources
        1. 6.5.1.1 Main Oscillator
          1. 6.5.1.1.1 Timing Requirements for Main Oscillator
        2. 6.5.1.2 Low-Power Oscillator
          1. 6.5.1.2.1 Features
          2. 6.5.1.2.2 LPO Electrical and Timing Specifications
        3. 6.5.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.5.1.3.1 Block Diagram
          2. 6.5.1.3.2 PLL Timing Specifications
      2. 6.5.2 Clock Domains
        1. 6.5.2.1 Clock Domain Descriptions
        2. 6.5.2.2 Mapping of Clock Domains to Device Modules
      3. 6.5.3 Clock Test Mode
    6. 6.6  Clock Monitoring
      1. 6.6.1 Clock Monitor Timings
      2. 6.6.2 External Clock (ECLK) Output Functionality
      3. 6.6.3 Dual Clock Comparator
        1. 6.6.3.1 Features
        2. 6.6.3.2 Mapping of DCC Clock Source Inputs
    7. 6.7  Glitch Filters
    8. 6.8  Device Memory Map
      1. 6.8.1 Memory Map Diagram
      2. 6.8.2 Memory Map Table
      3. 6.8.3 Master/Slave Access Privileges
    9. 6.9  Flash Memory
      1. 6.9.1 Flash Memory Configuration
      2. 6.9.2 Main Features of Flash Module
      3. 6.9.3 ECC Protection for Flash Accesses
      4. 6.9.4 Flash Access Speeds
    10. 6.10 Flash Program and Erase Timings for Program Flash
    11. 6.11 Flash Program and Erase Timings for Data Flash
    12. 6.12 Tightly Coupled RAM Interface Module
      1. 6.12.1 Features
      2. 6.12.2 TCRAMW ECC Support
    13. 6.13 Parity Protection for Accesses to peripheral RAMs
    14. 6.14 On-Chip SRAM Initialization and Testing
      1. 6.14.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.14.1.1 Features
        2. 6.14.1.2 PBIST RAM Groups
      2. 6.14.2 On-Chip SRAM Auto Initialization
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
    17. 6.17 Error Signaling Module
      1. 6.17.1 Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset / Abort / Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 MIBADC Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET Checking
        1. 7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)
      5. 7.4.5 Disabling N2HET Outputs
      6. 7.4.6 High-End Timer Transfer Unit (N2HET)
        1. 7.4.6.1 Features
        2. 7.4.6.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Multibuffered / Standard Serial Peripheral Interface
      1. 7.7.1 Features
      2. 7.7.2 MibSPI Transmit and Receive RAM Organization
      3. 7.7.3 MibSPI Transmit Trigger Events
        1. 7.7.3.1 MIBSPI1 Event Trigger Hookup
      4. 7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.7.5 SPI Slave Mode I/O Timings
    8. 7.8 Enhanced Quadrature Encoder (eQEP)
      1. 7.8.1 Clock Enable Control for eQEPx Modules
      2. 7.8.2 Using eQEPx Phase Error
      3. 7.8.3 Input Connections to eQEPx Modules
      4. 7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Getting Started
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
    7. 8.7 Device Identification Code Register
    8. 8.8 Die Identification Registers
    9. 8.9 Module Certifications
      1. 8.9.1 DCAN Certification
      2. 8.9.2 LIN Certifications
        1. 8.9.2.1 LIN Master Mode
        2. 8.9.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.9.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Addendum
    1. 9.1 Packaging Information

6 System Information and Electrical Specifications

6.1 Voltage Monitor Characteristics

A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.

6.1.1 Important Considerations

  • The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in reset when the voltage supplies are out of range.
  • The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.

6.1.2 Voltage Monitor Operation

The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good I/O signal (PGIO) on the device. During power up or power down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU being low isolates the core logic as well as the I/O controls during the power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.

When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.

The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.2.3.1 for the timing information on this glitch filter.

Table 6-1 Voltage Monitoring Specifications

PARAMETER MIN TYP MAX UNIT
VMON Voltage monitoring thresholds VCC low - VCC level below this threshold is detected as too low. 0.75 0.9 1.13 V
VCC high - VCC level above this threshold is detected as too high. 1.40 1.7 2.1
VCCIO low - VCCIO level below this threshold is detected as too low. 1.85 2.4 2.9

6.1.3 Supply Filtering

The VMON has the capability to filter glitches on the VCC and VCCIO supplies.

Table 6-2 shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.

Table 6-2 VMON Supply Glitch Filtering Capability

PARAMETER MIN MAX UNIT
Width of glitch on VCC that can be filtered 250 1000 ns
Width of glitch on VCCIO that can be filtered 250 1000 ns

6.2 Power Sequencing and Power-On Reset

6.2.1 Power-Up Sequence

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (for more details, see Table 6-4), core voltage rising above the minimum core supply threshold, and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.

During power up, the device goes through the sequential phases listed in Table 6-3.

Table 6-3 Power-Up Phases

Oscillator start-up and validity check 1032 oscillator cycles
eFuse autoload 1160 oscillator cycles
Flash pump power up 688 oscillator cycles
Flash bank power up 617 oscillator cycles
Total 3497 oscillator cycles

The CPU reset is released at the end of this sequence and fetches the first instruction from address 0x00000000.

6.2.2 Power-Down Sequence

The different supplies to the device can be powered down in any order.

6.2.3 Power-On Reset: nPORRST

This reset must be asserted by an external circuitry whenever the I/O or core supplies are outside the recommended range. This signal has a glitch filter on it. It also has an internal pulldown.

6.2.3.1 nPORRST Electrical and Timing Requirements

Table 6-4 Electrical Requirements for nPORRST

NO. PARAMETER MIN MAX UNIT
VCCPORL VCC low supply level when nPORRST must be active during power up 0.5 V
VCCPORH VCC high supply level when nPORRST must remain active during power up and become active during power down 1.14 V
VCCIOPORL VCCIO / VCCP low supply level when nPORRST must be active during power up 1.1 V
VCCIOPORH VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down 3.0 V
VIL(PORRST) Low-level input voltage of nPORRST VCCIO > 2.5 V 0.2 * VCCIO V
Low-level input voltage of nPORRST VCCIO < 2.5 V 0.5 V
3 tsu(PORRST) Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up 0 ms
6 th(PORRST) Hold time, nPORRST active after VCC > VCCPORH 1 ms
7 tsu(PORRST) Setup time, nPORRST active before VCC < VCCPORH during power down 2 µs
8 th(PORRST) Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH 1 ms
9 th(PORRST) Hold time, nPORRST active after VCC < VCCPORL 0 ms
tf(nPORRST) Filter time nPORRST pin;
Pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset.
475 2000 ns
TMS570LS0232 nporrst_timing_pns160.gifFigure 6-1 nPORRST Timing Diagram

6.3 Warm Reset (nRST)

This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.

This terminal has a glitch filter. It also has an internal pullup

6.3.1 Causes of Warm Reset

Table 6-5 Causes of Warm Reset

DEVICE EVENT SYSTEM STATUS FLAG
Power-up reset Exception Status Register, bit 15
Oscillator fail Global Status Register, bit 0
PLL slip Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset Exception Status Register, bit 13
CPU Reset (driven by the CPU STC) Exception Status Register, bit 5
Software reset Exception Status Register, bit 4
External reset Exception Status Register, bit 3

6.3.2 nRST Timing Requirements

Table 6-6 nRST Timing Requirements

MIN MAX UNIT
tv(RST) Valid time, nRST active after nPORRST inactive 2256tc(OSC)(1) ns
Valid time, nRST active (all other system reset conditions) 32tc(VCLK)
tf(nRST) Filter time nRST pin;
Pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset
475 2000 ns
(1) Assumes the oscillator has started up and stabilized before nPORRST is released.

6.4 ARM Cortex-R4 CPU Information

6.4.1 Summary of ARM Cortex-R4 CPU Features

The features of the ARM Cortex-R4 CPU include:

  • An integer unit with integral Embedded ICE-RT logic.
  • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
  • Dynamic branch prediction with a global history buffer, and a 4-entry return stack
  • Low interrupt latency.
  • Nonmaskable interrupt.
  • A Harvard Level one (L1) memory system with:
    • Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
    • ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions
  • Dual core logic for fault detection in safety-critical applications.
  • An L2 memory interface:
    • Single 64-bit master AXI interface
    • 64-bit slave AXI interface to TCM RAM blocks
  • A debug interface to a CoreSight Debug Access Port (DAP).
  • Six Hardware Breakpoints
  • Two Watchpoints
  • A Perfomance Monitoring Unit (PMU)
  • A Vectored Interrupt Controller (VIC) port.

For more information on the ARM Cortex-R4 CPU, see www.arm.com.

6.4.2 ARM Cortex-R4 CPU Features Enabled by Software

The following CPU features are disabled on reset and must be enabled by the application if required.

  • ECC On Tightly Coupled Memory (TCM) Accesses
  • Hardware Vectored Interrupt (VIC) Port
  • Memory Protection Unit (MPU)

6.4.3 Dual Core Implementation

The device has two Cortex-R4 cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by 2 clock cycles as shown in Figure 6-3.

The CPUs have a diverse CPU placement given by following requirements:

  • Different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
  • Dedicated guard ring for each CPU

TMS570LS0232 dual_cpu_orient.gifFigure 6-2 Dual - CPU Orientation

6.4.4 Duplicate clock tree after GCLK

The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the 2nd CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-3.

6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety

This device has two ARM Cortex-R4 CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in Figure 6-3.

TMS570LS0232 dual_core_implementation_pns160.gifFigure 6-3 Dual Core Implementation

To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.

6.4.6 CPU Self-Test

The CPU STC (Self-Test Controller) is used to test the two Cortex-R4 CPU Cores using the Deterministic Logic BIST Controller as the test engine.

The main features of the self-test controller are:

  • Ability to divide the complete test run into independent test intervals
  • Capable of running the complete test or running a few intervals at a time
  • Ability to continue from the last executed interval (test set) or to restart from the beginning (first test set)
  • Complete isolation of the self-tested CPU core from the rest of the system during the self-test run
  • Ability to capture the failure interval number
  • Timeout counter for the CPU self-test run as a fail-safe feature

6.4.6.1 Application Sequence for CPU Self-Test

  1. Configure clock domain frequencies.
  2. Select the number of test intervals to be run.
  3. Configure the timeout period for the self-test run.
  4. Save the CPU state if required
  5. Enable self-test.
  6. Wait for CPU reset.
  7. In the reset handler, read CPU self-test status to identify any failures.
  8. Retrieve CPU state if required.

For more information, see the TMS570LS0232 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU603).

6.4.6.2 CPU Self-Test Clock Configuration

The maximum clock rate for the self-test is 45 MHz. The STCCLK is divided down from the CPU clock, when necessary. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.

6.4.6.3 CPU Self-Test Coverage

Table 6-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.

Table 6-7 CPU Self-Test Coverage

INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 60.06 1365
2 68.71 2730
3 73.35 4095
4 76.57 5460
5 78.7 6825
6 80.4 8190
7 81.76 9555
8 82.94 10920
9 83.84 12285
10 84.58 13650
11 85.31 15015
12 85.9 16380
13 86.59 17745
14 87.17 19110
15 87.67 20475
16 88.11 21840
17 88.53 23205
18 88.93 24570
19 89.26 25935
20 89.56 27300
21 89.86 28665
22 90.1 30030
23 90.36 31395
24 90.62 32760
25 90.86 34125
26 91.06 35490

6.5 Clocks

6.5.1 Clock Sources

The table below lists the available clock sources on the device. Each of the clock sources can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.

The table also shows the default state of each clock source.

Table 6-8 Available Clock Sources

CLOCK
SOURCE NO.
NAME DESCRIPTION DEFAULT STATE
0 OSCIN Main Oscillator Enabled
1 PLL1 Output From PLL1 Disabled
2 Reserved Reserved Disabled
3 EXTCLKIN1 External Clock Input #1 Disabled
4 CLK80K Low-Frequency Output of Internal Reference Oscillator Enabled
5 CLK10M High-Frequency Output of Internal Reference Oscillator Enabled
6 Reserved Reserved Disabled
7 Reserved Reserved Disabled

6.5.1.1 Main Oscillator

The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.

TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.

An external oscillator source can be used by connecting a 3.3 V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 6-4.

TMS570LS0232 clock_connection_pns160.gifFigure 6-4 Recommended Crystal/Clock Connection

6.5.1.1.1 Timing Requirements for Main Oscillator

Table 6-9 Timing Requirements for Main Oscillator

PARAMETER MIN TYP MAX UNIT
tc(OSC) Cycle time, OSCIN (when using a sine-wave input) 50 200 ns
tc(OSC_SQR) Cycle time, OSCIN, (when input to the OSCIN is a square wave ) 50 200 ns
tw(OSCIL) Pulse duration, OSCIN low (when input to the OSCIN is a square wave) 15 ns
tw(OSCIH) Pulse duration, OSCIN high (when input to the OSCIN is a square wave) 15 ns

6.5.1.2 Low-Power Oscillator

The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO.

6.5.1.2.1 Features

The main features of the LPO are:

  • Supplies a clock at extremely low power for power-saving modes. This is connected as clock source # 4 of the Global Clock Module.
  • Supplies a high-frequency clock for nontiming-critical systems. This is connected as clock source # 5 of the Global Clock Module.
  • Provides a comparison clock for the crystal oscillator failure detection circuit.

TMS570LS0232 LPO_Block_Diagram_pns160.gifFigure 6-5 LPO Block Diagram

Figure 6-5 shows a block diagram of the internal reference oscillator. This is an LPO and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.

6.5.1.2.2 LPO Electrical and Timing Specifications

Table 6-10 LPO Specifications

PARAMETER MIN TYP MAX UNIT
Clock Detection Oscillator fail frequency - lower threshold, using untrimmed LPO output 1.375 2.4 4.875 MHz
Oscillator fail frequency - higher threshold, using untrimmed LPO output 22 38.4 78
LPO - HF oscillator (fHFLPO) Untrimmed frequency 5.5 9 19.5 MHz
Trimmed frequency 8 9.6 11 MHz
Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs) 10 µs
Cold start-up time 900 µs
LPO - LF oscillator (fLFLPO) Untrimmed frequency 36 85 180 kHz
Start-up time from STANDBY (LPO BIAS_EN High for at least 900 µs) 100 µs
Cold start-up time 2000 µs

6.5.1.3 Phase Locked Loop (PLL) Clock Modules

The PLL is used to multiply the input frequency to some higher frequency.

The main features of the PLL are:

  • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL.
  • Configurable frequency multipliers and dividers.
  • Built-in PLL Slip monitoring circuit.
  • Option to reset the device on a PLL slip detection.

6.5.1.3.1 Block Diagram

Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.

TMS570LS0232 FMzPLLx_block_diagram_1oscin_pns160.gifFigure 6-6 PLL Block Diagram

6.5.1.3.2 PLL Timing Specifications

Table 6-11 PLL Timing Specifications

PARAMETER MIN MAX UNIT
fINTCLK PLL1 Reference Clock frequency 1 20 MHz
fpost_ODCLK Post-ODCLK – PLL1 Post-divider input clock frequency 400 MHz
fVCOCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency 150 550 MHz

6.5.2 Clock Domains

6.5.2.1 Clock Domain Descriptions

Table 6-12 lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.

Table 6-12 Clock Domain Descriptions

CLOCK DOMAIN NAME DEFAULT CLOCK SOURCE CLOCK SOURCE SELECTION REGISTER DESCRIPTION
HCLK OSCIN GHVSRC
  • Is disabled through the CDDISx registers bit 1
GCLK OSCIN GHVSRC
  • Always the same frequency as HCLK
  • In phase with HCLK
  • Is disabled separately from HCLK through the CDDISx registers bit 0
  • Can be divided by 1 up to 8 when running CPU self-test (LBIST) using the CLKDIV field of the STCCLKDIV register at address 0xFFFFE108
GCLK2 OSCIN GHVSRC
  • Always the same frequency as GCLK
  • 2 cycles delayed from GCLK
  • Is disabled along with GCLK
  • Gets divided by the same divider setting as that for GCLK when running CPU self-test (LBIST)
VCLK OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Is disabled separately from HCLK through the CDDISx registers bit 2
  • Can be disabled separately for eQEP using CDDISx registers bit 9
VCLK2 OSCIN GHVSRC
  • Divided down from HCLK
  • Can be HCLK/1, HCLK/2, ... or HCLK/16
  • Frequency must be an integer multiple of VCLK frequency
  • Is disabled separately from HCLK through the CDDISx registers bit 3
VCLKA1 VCLK VCLKASRC
  • Defaults to VCLK as the source
  • Frequency can be as fast as HCLK frequency
  • Is disabled through the CDDISx registers bit 4
RTICLK VCLK RCLKSRC
  • Defaults to VCLK as the source
  • If a clock source other than VCLK is selected for RTICLK, then the RTICLK frequency must be less than or equal to VCLK/3
    • Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary
  • Is disabled through the CDDISx registers bit 6

6.5.2.2 Mapping of Clock Domains to Device Modules

Each clock domain has a dedicated functionality as shown in the figure below.

TMS570LS0232 dev_clock_domains_f3_spns186.gifFigure 6-7 Device Clock Domains

6.5.3 Clock Test Mode

The TMS570 platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET[2] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module.

Table 6-13 Clock Test Mode Options

CLKTEST[3-0] SIGNAL ON ECLK CLKTEST[11-8] SIGNAL ON N2HET[2]
0000 Oscillator 0000 Oscillator Valid Status
0001 Main PLL free-running clock output (PLLCLK) 0001 Main PLL Valid status
0010 Reserved 0010 Reserved
0011 Reserved 0011 Reserved
0100 CLK80K 0100 Reserved
0101 CLK10M 0101 CLK10M Valid status
0110 Reserved 0110 Reserved
0111 Reserved 0111 Reserved
1000 GCLK 1000 CLK80K
1001 RTI Base 1001 Oscillator Valid status
1010 Reserved 1010 Oscillator Valid status
1011 VCLKA1 1011 Oscillator Valid status
1100 Reserved 1100 Oscillator Valid status
1101 Reserved 1101 Oscillator Valid status
1110 Reserved 1110 Oscillator Valid status
1111 Flash HD Pump Oscillator 1111 Oscillator Valid status

6.6 Clock Monitoring

The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal low-power oscillator (LPO).

The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).

The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).

The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.

6.6.1 Clock Monitor Timings

For more information on LPO and Clock detection, refer to Table 6-10.

TMS570LS0232 LPO_Clk_Detection_pns160.gifFigure 6-8 LPO and Clock Detection, Untrimmed HFLPO

6.6.2 External Clock (ECLK) Output Functionality

The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.

6.6.3 Dual Clock Comparator

The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC can be configured to use CLK10M as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC to monitor the PLL output clock when VCLK is using the PLL output as its source.

6.6.3.1 Features

  • Takes two different clock sources as input to two independent counter blocks.
  • One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
  • Each counter block is programmable with initial, or seed values.
  • The counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the CPU.

6.6.3.2 Mapping of DCC Clock Source Inputs

Table 6-14 DCC Counter 0 Clock Sources

TEST MODE CLOCK SOURCE [3:0] CLOCK NAME
0 Others Oscillator (OSCIN)
0x5 High-frequency LPO
0xA Test clock (TCK)
1 X VCLK

Table 6-15 DCC Counter 1 Clock Sources

TEST MODE KEY [3:0] CLOCK SOURCE [3:0] CLOCK NAME
0 Others N2HET[31]
0x0 Main PLL free-running clock output
0x1 n/a
0x2 Low-frequency LPO
0xA 0x3 High-frequency LPO
0x4 Flash HD pump oscillator
0x5 EXTCLKIN
0x6 n/a
0x7 Ring oscillator
0x8 - 0xF VCLK
1 X X HCLK

6.7 Glitch Filters

A glitch filter is present on the following signals.

Table 6-16 Glitch Filter Timing Specifications

PIN PARAMETER MIN MAX UNIT
nPORRST tf(nPORRST)

Filter time nPORRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset(1)

475 2000 ns
nRST tf(nRST)

Filter time nRST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset

475 2000 ns
TEST tf(TEST)

Filter time TEST pin;

pulses less than MIN will be filtered out, pulses greater than MAX will pass through

475 2000 ns
(1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, and so forth) without also generating a valid reset signal to the CPU.

6.8 Device Memory Map

6.8.1 Memory Map Diagram

Figure 6-9 shows the device memory map.

TMS570LS0232 memory_map_f7_f8_spns240_242.gifFigure 6-9 TMS570LS0232 Memory Map

The Flash memory in all configurations is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.

6.8.2 Memory Map Table

See Figure 1-1 for a block diagram showing the device interconnects.

Table 6-17 Device Memory Map

MODULE NAME FRAME CHIP
SELECT
ADDRESS RANGE FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
Memories tightly coupled to the ARM Cortex-R4 CPU
TCM Flash CS0 0x0000_0000 0x00FF_FFFF 16MB 128KB Abort
TCM RAM + RAM ECC CSRAM0 0x0800_0000 0x0BFF_3FFF 64MB 32KB
Mirrored Flash Flash mirror frame 0x2000_0000 0x20FF_FFFF 16MB 128KB
Flash Module Bus2 Interface
Customer OTP, TCM Flash Banks 0xF000_0000 0xF000_07FF 64KB 2KB Abort
Customer OTP, EEPROM Bank 0xF000_E000 0xF000_E3FF 1KB
Customer OTP–ECC, TCM Flash Banks 0xF004_0000 0xF004_00FF 8KB 256B
Customer OTP–ECC, EEPROM Bank 0xF004_1C00 0xF004_1C7F 128B
TI OTP, TCM Flash Banks 0xF008_0000 0xF008_07FF 64KB 2KB
TI OTP, EEPROM Bank 0xF008_E000 0xF008_E3FF 1KB
TI OTP–ECC, TCM Flash Banks 0xF00C_0000 0xF00C_00FF 8KB 256B
TI OTP–ECC, EEPROM Bank 0xF00C_1C00 0xF00C_1C7F 128B
EEPROM Bank–ECC 0xF010_0000 0xF010_07FF 256KB 2KB
EEPROM Bank 0xF020_0000 0xF020_3FFF 2MB 16KB
Flash Data Space ECC 0xF040_0000 0xF040_DFFF 1MB 48KB
Cyclic Redundancy Checker (CRC) Module Registers
CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128KB 2KB Abort for accesses above 2KB
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128KB 2KB Wrap around for accesses to unimplemented address offsets lower than 0x7FF. Abort generated for accesses beyond offset 0x800.
MIBADC RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128KB 8KB Wrap around for accesses to unimplemented address offsets lower than 0x1FFF.
MIBADC Look-Up Table 384 bytes Look-up table for ADC wrapper. Starts at offset 0x2000 ans ends at 0x217F. Wrap around for accesses between offsets 0x180 and 0x3FFF. Aborts generated for accesses beyond 0x4000
N2HET RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128KB 16KB Wrap around for accesses to unimplemented address offsets lower than 0x3FFF. Abort generated for accesses beyond 0x3FFF.
HTU RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128KB 1KB Abort
Debug Components
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4 Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect
Peripheral Control Registers
HTU PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B Reads return zeros, writes have no effect
N2HET PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B Reads return zeros, writes have no effect
GIO PS[16] 0xFFF7_BC00 0xFFF7_BCFF 256B 256B Reads return zeros, writes have no effect
MIBADC PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B Reads return zeros, writes have no effect
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B Reads return zeros, writes have no effect
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B Reads return zeros, writes have no effect
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return zeros, writes have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return zeros, writes have no effect
SPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return zeros, writes have no effect
SPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return zeros, writes have no effect
EQEP PS[25] 0xFFF7_9900 0xFFF7_99FF 256B 256B Reads return zeros, writes have no effect
EQEP (Mirrored) PS2[25] 0xFCF7_9900 0xFCF7_99FF 256B 256B Reads return zeros, writes have no effect
System Modules Control Registers and Memories
VIM RAM PPCS2 0xFFF8_2000 0xFFF8_2FFF 4KB 1KB Wrap around for accesses to unimplemented address offsets lower than 0x3FF. Accesses beyond 0x3FF will be ignored.
Flash Wrapper PPCS7 0xFFF8_7000 0xFFF8_7FFF 4KB 4KB Abort
eFuse Farm Controller PPCS12 0xFFF8_C000 0xFFF8_CFFF 4KB 4KB Abort
PCR registers PPS0 0xFFFF_E000 0xFFFF_E0FF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 2 (see device TRM) PPS0 0xFFFF_E100 0xFFFF_E1FF 256B 256B Reads return zeros, writes have no effect
PBIST PPS1 0xFFFF_E400 0xFFFF_E5FF 512B 512B Reads return zeros, writes have no effect
STC PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B Reads return zeros, writes have no effect
IOMM Multiplexing control module PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B Generates address error interrupt if enabled.
DCC PPS3 0xFFFF_EC00 0xFFFF_ECFF 256B 256B Reads return zeros, writes have no effect
ESM PPS5 0xFFFF_F500 0xFFFF_F5FF 256B 256B Reads return zeros, writes have no effect
CCMR4 PPS5 0xFFFF_F600 0xFFFF_F6FF 256B 256B Reads return zeros, writes have no effect
RAM ECC even PPS6 0xFFFF_F800 0xFFFF_F8FF 256B 256B Reads return zeros, writes have no effect
RAM ECC odd PPS6 0xFFFF_F900 0xFFFF_F9FF 256B 256B Reads return zeros, writes have no effect
RTI + DWWD PPS7 0xFFFF_FC00 0xFFFF_FCFF 256B 256B Reads return zeros, writes have no effect
VIM Parity PPS7 0xFFFF_FD00 0xFFFF_FDFF 256B 256B Reads return zeros, writes have no effect
VIM PPS7 0xFFFF_FE00 0xFFFF_FEFF 256B 256B Reads return zeros, writes have no effect
System Module - Frame 1 (see device TRM) PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B Reads return zeros, writes have no effect

6.8.3 Master/Slave Access Privileges

The table below lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.

Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed in the "MASTERS" column can access that slave module.

Table 6-18 Master / Slave Access Matrix

MASTERS ACCESS MODE SLAVES ON MAIN SCR
Flash Module Bus2 Interface:
OTP, ECC, EEPROM Bank
Non-CPU Accesses to Program Flash and CPU Data RAM CRC Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories
CPU READ User/Privilege Yes Yes Yes Yes
CPU WRITE User/Privilege No Yes Yes Yes
HTU Privilege No Yes Yes Yes

6.9 Flash Memory

6.9.1 Flash Memory Configuration

Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.

Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.

Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.

Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.

Note: The memory region from 0x0002_0000 to 0x0003_FFFF is not inherently protected against creating nERROR pin toggles from speculative fetches or from run away code. An MPU region must be used to limit accesses to only the first 128KB of ATCM space (0x0000_0000-0x0001_FFFF). Also, Flash API version 02.01.01 or later should be used to program or erase the flash of this device.

Table 6-19 Flash Memory Banks and Sectors

MEMORY ARRAYS (or BANKS) SECTOR
NO.
SEGMENT LOW ADDRESS HIGH ADDRESS
BANK0 (128KB)(1) 0 8KB 0x0000_0000 0x0000_1FFF
1 8KB 0x0000_2000 0x0000_3FFF
2 8KB 0x0000_4000 0x0000_5FFF
3 8KB 0x0000_6000 0x0000_7FFF
4 8KB 0x0000_8000 0x0000_9FFF
5 8KB 0x0000_A000 0x0000_BFFF
6 8KB 0x0000_C000 0x0000_DFFF
7 8KB 0x0000_E000 0x0000_FFFF
8 8KB 0x0001_0000 0x0001_1FFF
9 8KB 0x0001_2000 0x0001_3FFF
10 8KB 0x0001_4000 0x0001_5FFF
11 8KB 0x0001_6000 0x0001_7FFF
12 32KB 0x0001_8000 0x0001_FFFF
BANK7 (16KB) for EEPROM emulation(2)(3) 0 4KB 0xF020_0000 0xF020_0FFF
1 4KB 0xF020_1000 0xF020_1FFF
2 4KB 0xF020_2000 0xF020_2FFF
3 4KB 0xF020_3000 0xF020_3FFF
(1) This Flash bank is 144-bit wide with ECC support.
(2) Flash bank7 is an FLEE bank and can be programmed while executing code from flash bank0. It is 72-bit wide with ECC support.
(3) Code execution is not allowed from flash bank7.

6.9.2 Main Features of Flash Module

  • Support for multiple flash banks for program and/or data storage
  • Simultaneous read access on a bank while performing program or erase operation on any other bank
  • Integrated state machines to automate flash erase and program operations
  • Software interface for flash program and erase operations
  • Pipelined mode operation to improve instruction access interface bandwidth
  • Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4 CPU
    • Error address is captured for host system debugging
  • Support for a rich set of diagnostic features

6.9.3 ECC Protection for Flash Accesses

All accesses to the program flash memory are protected by Single Error Correction Double Error Detection (SECDED) logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.

MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor statesORR r1, r1, #0x00000010MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC registerMRC p15,#0,r1,c9,c12,#0

The application must also explicitly enable the CPU's ECC checking for accesses on the CPU's ATCM and BTCM interfaces. These are connected to the program flash and data RAM respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN and ATCMPCEN bits of the System Control coprocessor's Auxiliary Control Register, c1.

MRC p15, #0, r1, c1, c0, #1ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMsDMBMCR p15, #0, r1, c1, c0, #1

6.9.4 Flash Access Speeds

For information on flash memory access speeds and the relevant wait states required, see Section 5.6.

6.10 Flash Program and Erase Timings for Program Flash

Table 6-20 Timing Specifications for Program Flash

PARAMETER MIN NOM MAX UNIT
tprog (144bit) Wide Word (144 bit) programming time 40 300 µs
tprog (Total) 384KByte programming time(1) -40°C to 125°C 4 s
0°C to 60°C, for first 25 cycles 1 2
terase Sector/Bank erase time(2) -40°C to 125°C 0.30 4 s
0°C to 60°C, for first 25 cycles 16 100 ms
twec Write/erase cycles with 15 year Data Retention requirement -40°C to 125°C 1000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 144 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.11 Flash Program and Erase Timings for Data Flash

Table 6-21 Timing Specifications for Data Flash

PARAMETER MIN NOM MAX UNIT
tprog (72 bit) Wide Word (72 bit) programming time 47 300 µs
tprog (Total) 16KB programming time(1) –40°C to 125°C 330 ms
0°C to 60°C, for first 25 cycles 100 165
terase Sector/Bank erase time(2) –40°C to 125°C 0.200 8 s
0°C to 60°C, for first 25 cycles 14 100 ms
twec Write/erase cycles with 15 year Data Retention requirement –40°C to 125°C 100000 cycles
(1) This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes programming 72 bits at a time at the maximum specified operating frequency.
(2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector.

6.12 Tightly Coupled RAM Interface Module

Figure 6-10 illustrates the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4 CPU.

TMS570LS0232 tcram_fbd_144pin_spns186.gifFigure 6-10 TCRAM Block Diagram

6.12.1 Features

The features of the Tightly Coupled RAM (TCRAM) module are:

  • Acts as slave to the BTCM interface of the Cortex-R4 CPU
  • Supports CPU's internal ECC scheme by providing 64-bit data and 8-bit ECC code
  • Monitors CPU Event Bus and generates single-bit or multibit error interrupts
  • Stores addresses for single-bit and multibit errors
  • Provides CPU address bus integrity checking by supporting parity checking on the address bus
  • Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
  • Provides enhanced safety for the RAM addressing by implementing two 36-bit wide byte-interleaved RAM banks and generating independent RAM access control signals to the two banks
  • Supports auto-initialization of the RAM banks along with the ECC bits
  • No support for bit-wise RAM accesses

6.12.2 TCRAMW ECC Support

The TCRAMW passes on the ECC code for each data read by the Cortex-R4 CPU from the RAM. It also stores the CPU's ECC port contents in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU's event bus and provides registers for indicating single-bit and multibit errors and also for identifying the address that caused the single-bit or multibit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.

For more information see the device Technical Reference Manual.

6.13 Parity Protection for Accesses to peripheral RAMs

Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.

6.14 On-Chip SRAM Initialization and Testing

6.14.1 On-Chip SRAM Self-Test Using PBIST

6.14.1.1 Features

  • Extensive instruction set to support various memory test algorithms
  • ROM-based algorithms allow the application to run TI production-level memory tests
  • Independent testing of all on-chip SRAM

6.14.1.2 PBIST RAM Groups

Table 6-22 PBIST RAM Grouping

MEMORY RAM GROUP TEST CLOCK MEM TYPE TEST PATTERN (ALGORITHM)
TRIPLE READ
SLOW READ
TRIPLE READ
FAST READ
MARCH 13N(1)
TWO PORT (CYCLES)
MARCH 13N(1)
SINGLE PORT (CYCLES)
ALGO MASK 0x1 ALGO MASK 0x2 ALGO MASK 0x4 ALGO MASK 0x8
PBIST_ROM 1 ROM CLK ROM X X
STC_ROM 2 ROM CLK ROM X X
DCAN1 3 VCLK Dual Port 12720
DCAN2 4 VCLK Dual Port 6480
RAM 6 HCLK Single Port 133160
MIBSPI1 7 VCLK Dual Port 33440
VIM 10 VCLK Dual Port 12560
MIBADC 11 VCLK Dual Port 4200
N2HET1 13 VCLK Dual Port 25440
HTU1 14 VCLK Dual Port 6480
(1) There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for application testing.

The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.

6.14.2 On-Chip SRAM Auto Initialization

This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).

The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.

For more information on these registers refer to the device Technical Reference Manual.

The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-23.

Table 6-23 Memory Initialization

CONNECTING MODULE ADDRESS RANGE MSINENA REGISTER
BIT NO.(1)
BASE ADDRESS ENDING ADDRESS
RAM 0x08000000 0x08007FFF 0
MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF  7(2)
DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6
DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5
MIBADC RAM 0xFF3E0000 0xFF3FFFFF 8
N2HET RAM 0xFF460000 0xFF47FFFF 3
HTU RAM 0xFF4E0000 0xFF4FFFFF 4
VIM RAM 0xFFF82000 0xFFF82FFF 2
(1) Unassigned register bits are reserved.
(2) The MibSPI1 module performs an initialization of the transmit and receive RAMs as soon as the module is brought out of reset using the SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using the system module auto-initialization method.

6.15 Vectored Interrupt Manager

The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the central processing unit (CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).

6.15.1 VIM Features

The VIM module has the following features:

  • Supports 96 interrupt channels.
    • Provides programmable priority and enable for interrupt request lines.
  • Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
  • Provides two software dispatch mechanisms when the CPU VIC port is not used.
    • Index interrupt
    • Register vectored interrupt
  • Parity protected vector interrupt table against soft errors.

6.15.2 Interrupt Request Assignments

Table 6-24 Interrupt Request Assignments

MODULES INTERRUPT SOURCES DEFAULT VIM
INTERRUPT CHANNEL
ESM ESM High level interrupt (NMI) 0
Reserved Reserved 1
RTI RTI compare interrupt 0 2
RTI RTI compare interrupt 1 3
RTI RTI compare interrupt 2 4
RTI RTI compare interrupt 3 5
RTI RTI overflow interrupt 0 6
RTI RTI overflow interrupt 1 7
Reserved Reserved 8
GIO GIO interrupt A 9
N2HET N2HET level 0 interrupt 10
HTU HTU level 0 interrupt 11
MIBSPI1 MIBSPI1 level 0 interrupt 12
LIN LIN level 0 interrupt 13
MIBADC MIBADC event group interrupt 14
MIBADC MIBADC sw group 1 interrupt 15
DCAN1 DCAN1 level 0 interrupt 16
SPI2 SPI2 level 0 interrupt 17
Reserved Reserved 18
Reserved Reserved 19
ESM ESM Low level interrupt 20
SYSTEM Software interrupt (SSI) 21
CPU PMU interrupt 22
GIO GIO interrupt B 23
N2HET N2HET level 1 interrupt 24
HTU HTU level 1 interrupt 25
MIBSPI1 MIBSPI1 level 1 interrupt 26
LIN LIN level 1 interrupt 27
MIBADC MIBADC sw group 2 interrupt 28
DCAN1 DCAN1 level 1 interrupt 29
SPI2 SPI2 level 1 interrupt 30
MIBADC MIBADC magnitude compare interrupt 31
Reserved Reserved 32-34
DCAN2 DCAN2 level 0 interrupt 35
Reserved Reserved 36
SPI3 SPI3 level 0 interrupt 37
SPI3 SPI3 level 1 interrupt 38
Reserved Reserved 39-41
DCAN2 DCAN2 level 1 interrupt 42
Reserved Reserved 43-60
FMC FSM_DONE interrupt 61
Reserved Reserved 62-79
HWAG HWA_INT_REQ_H 80
Reserved Reserved 81
DCC DCC done interrupt 82
Reserved Reserved 83
eQEPINTn eQEP Interrupt 84
PBIST PBIST Done Interrupt 85
Reserved Reserved 86-87
HWAG HWA_INT_REQ_L 88
Reserved Reserved 89-95

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..94 can be used and are offset by 1 address in the VIM RAM.

6.16 Real-Time Interrupt Module

The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the timebases needed for scheduling an operating system.

The timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values.

6.16.1 Features

The RTI module has the following features:

  • Two independent 64 bit counter blocks
  • Four configurable compares for generating operating system ticks. Each event can be driven by either counter block 0 or counter block 1.
  • Fast enabling/disabling of events
  • Two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block

6.16.2 Block Diagrams

Figure 6-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical.

TMS570LS0232 rti_counter_bd_pns186.gifFigure 6-11 Counter Block Diagram

Figure 6-12 shows a typical high-level block diagram for one of the four compares inside the RTI module. Each of the four compares are identical.

TMS570LS0232 rti_compare_bd_spns186.gifFigure 6-12 Compare Block Diagram

6.16.3 Clock Source Options

The RTI module uses the RTICLK clock domain for generating the RTI time bases.

The application can select the clock source for the RTICLK by configuring the RCLKSRC register in the System module at address 0xFFFFFF50. The default source for RTICLK is VCLK.

For more information, on the clock sources see Table 6-8 and Table 6-12.

6.17 Error Signaling Module

The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. This can be used as an indicator to an external monitor circuit to put the system into a safe state.

6.17.1 Features

The features of the Error Signaling Module are:

  • 128 interrupt/error channels are supported, divided into 3 different groups
    • 64 channels with maskable interrupt and configurable error pin behavior
    • 32 error channels with nonmaskable interrupt and predefined error pin behavior
    • 32 channels with predefined error pin behavior only
  • Error pin to signal severe device failure
  • Configurable timebase for error signal
  • Error forcing capability

6.17.2 ESM Channel Assignments

The Error Signaling Module (ESM) integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-26 shows the channel assignment for each group.

Table 6-25 ESM Groups

ERROR GROUP INTERRUPT CHARACTERISTICS INFLUENCE ON ERROR PIN
Group1 Maskable, low or high priority Configurable
Group2 Nonmaskable, high priority Fixed
Group3 No interrupt generated Fixed

Table 6-26 ESM Channel Assignments

ERROR SOURCES GROUP CHANNELS
Reserved Group1 0
Reserved Group1 1
Reserved Group1 2
Reserved Group1 3
Reserved Group1 4
Reserved Group1 5
FMC - correctable error: bus1 and bus2 interfaces (does not include accesses to EEPROM bank) Group1 6
N2HET - parity Group1 7
HTU - parity Group1 8
HTU - MPU Group1 9
PLL - Slip Group1 10
Clock Monitor - interrupt Group1 11
Reserved Group1 12
Reserved Group1 13
Reserved Group1 14
VIM RAM - parity Group1 15
Reserved Group1 16
MibSPI1 - parity Group1 17
Reserved Group1 18
MibADC - parity Group1 19
Reserved Group1 20
DCAN1 - parity Group1 21
Reserved Group1 22
DCAN2 - parity Group1 23
Reserved Group1 24
Reserved Group1 25
RAM even bank (B0TCM) - correctable error Group1 26
CPU - self-test Group1 27
RAM odd bank (B1TCM) - correctable error Group1 28
Reserved Group1 29
DCC - error Group1 30
CCM-R4 - self-test Group1 31
Reserved Group1 32
Reserved Group1 33
Reserved Group1 34
FMC - correctable error (EEPROM bank access) Group1 35
FMC - uncorrectable error (EEPROM bank access) Group1 36
IOMM - Mux configuration error Group1 37
Reserved Group1 38
Reserved Group1 39
eFuse farm – this error signal is generated whenever any bit in the eFuse farm error status register is set. The application can choose to generate and interrupt whenever this bit is set in order to service any eFuse farm error condition. Group1 40
eFuse farm - self test error. It is not necessary to generate a separate interrupt when this bit gets set. Group1 41
Reserved Group1 42
Reserved Group1 43
Reserved Group1 44
Reserved Group1 45
Reserved Group1 46
Reserved Group1 47
Reserved Group1 48
Reserved Group1 49
Reserved Group1 50
Reserved Group1 51
Reserved Group1 52
Reserved Group1 53
Reserved Group1 54
Reserved Group1 55
Reserved Group1 56
Reserved Group1 57
Reserved Group1 58
Reserved Group1 59
Reserved Group1 60
Reserved Group1 61
Reserved Group1 62
Reserved Group1 63
Reserved Group2 0
Reserved Group2 1
CCMR4 - compare Group2 2
Reserved Group2 3
FMC - uncorrectable error (address parity on bus1 accesses) Group2 4
Reserved Group2 5
RAM even bank (B0TCM) - uncorrectable error Group2 6
Reserved Group2 7
RAM odd bank (B1TCM) - uncorrectable error Group2 8
Reserved Group2 9
RAM even bank (B0TCM) - address bus parity error Group2 10
Reserved Group2 11
RAM odd bank (B1TCM) - address bus parity error Group2 12
Reserved Group2 13
Reserved Group2 14
Reserved Group2 15
TCM - ECC live lock detect Group2 16
Reserved Group2 17
Reserved Group2 18
Reserved Group2 19
Reserved Group2 20
Reserved Group2 21
Reserved Group2 22
Reserved Group2 23
RTI_WWD_NMI Group2 24
Reserved Group2 25
Reserved Group2 26
Reserved Group2 27
Reserved Group2 28
Reserved Group2 29
Reserved Group2 30
Reserved Group2 31
Reserved Group3 0
eFuse Farm - autoload error Group3 1
Reserved Group3 2
RAM even bank (B0TCM) - ECC uncorrectable error Group3 3
Reserved Group3 4
RAM odd bank (B1TCM) - ECC uncorrectable error Group3 5
Reserved Group3 6
FMC - uncorrectable error: bus1 and bus2 interfaces (does not include address parity error and errors on accesses to EEPROM bank) Group3 7
Reserved Group3 8
Reserved Group3 9
Reserved Group3 10
Reserved Group3 11
Reserved Group3 12
Reserved Group3 13
Reserved Group3 14
Reserved Group3 15
Reserved Group3 16
Reserved Group3 17
Reserved Group3 18
Reserved Group3 19
Reserved Group3 20
Reserved Group3 21
Reserved Group3 22
Reserved Group3 23
Reserved Group3 24
Reserved Group3 25
Reserved Group3 26
Reserved Group3 27
Reserved Group3 28
Reserved Group3 29
Reserved Group3 30
Reserved Group3 31

6.18 Reset / Abort / Error Sources

Table 6-27 Reset/Abort/Error Sources

ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP
GROUP.CHANNEL
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) n/a
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM → nERROR 3.3
B0 TCM (even) uncorrectable error (that is, redundant address decode) User/Privilege ESM → NMI → nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM → NMI → nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM → nERROR 3.5
B1 TCM (odd) uncorrectable error (that is, redundant address decode) User/Privilege ESM → NMI → nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM → NMI → nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to EEPROM bank) User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
User/Privilege Abort (CPU), ESM → nERROR 3.7
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank accesses)
User/Privilege ESM → nERROR 3.7
FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM → NMI → nERROR 2.4
FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36
HIGH-END TIMER TRANSFER UNIT (HTU)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt → VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt → VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET
Memory parity error User/Privilege ESM 1.7
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MIBADC
MibADC Memory parity error User/Privilege ESM 1.19
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
PLL
PLL slip error User/Privilege ESM 1.10
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC error User/Privilege ESM 1.30
CCM-R4
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM → NMI → nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELF-TEST (LBIST)
CPU Self-test (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM → nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU.
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.

6.19 Digital Windowed Watchdog

This device includes a digital windowed watchdog (DWWD) module that protects against runaway code execution.

The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or a nonmaskable interrupt to the CPU in case of a watchdog violation.

The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset.

6.20 Debug Subsystem

6.20.1 Block Diagram

The device contains an ICEPICK module to allow JTAG access to the scan chains (see Figure 6-13).

TMS570LS0232 debug_subsystem_f3_pns186.gifFigure 6-13 Debug Subsystem Block Diagram

6.20.2 Debug Components Memory Map

Table 6-28 Debug Components Memory Map

MODULE NAME FRAME CHIP
SELECT
FRAME ADDRESS RANGE FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME
START END
CoreSight Debug ROM CSCS0 0xFFA0_0000 0xFFA0_0FFF 4KB 4KB Reads return zeros, writes have no effect
Cortex-R4 Debug CSCS1 0xFFA0_1000 0xFFA0_1FFF 4KB 4KB Reads return zeros, writes have no effect

6.20.3 JTAG Identification Code

The JTAG ID code for this device is the same as the device ICEPick Identification Code.

Table 6-29 JTAG Identification Code

SILICON REVISION IDENTIFICATION CODE
Initial Silicon 0x0B97102F
Revision A 0x1B97102F
Revision B 0x2B97102F

6.20.4 Debug ROM

The Debug ROM stores the location of the components on the Debug APB bus:

Table 6-30 Debug ROM table

ADDRESS DESCRIPTION VALUE
0x000 Pointer to Cortex-R4 0x0000 1003
0x001 Reserved 0x0000 2002
0x002 Reserved 0x0000 3002
0x003 Reserved 0x0000 4002
0x004 End of table 0x0000 0000

6.20.5 JTAG Scan Interface Timings

Table 6-31 JTAG Scan Interface Timing(1)

NO. PARAMETER MIN MAX UNIT
fTCK TCK frequency (at HCLKmax) 12 MHz
fRTCK RTCK frequency (at TCKmax and HCLKmax) 10 MHz
1 td(TCK -RTCK) Delay time, TCK to RTCK 24 ns
2 tsu(TDI/TMS - RTCKr) Setup time, TDI, TMS before RTCK rise (RTCKr) 26 ns
3 th(RTCKr -TDI/TMS) Hold time, TDI, TMS after RTCKr 0 ns
4 th(RTCKr -TDO) Hold time, TDO after RTCKf 0 ns
5 td(TCKf -TDO) Delay time, TDO valid after RTCK fall (RTCKf) 12 ns
(1) Timings for TDO are specified for a maximum of 50 pF load on TDO
TMS570LS0232 jtag_timing_pns160.gifFigure 6-14 JTAG Timing

6.20.6 Advanced JTAG Security Module

This device includes a an Advanced JTAG Security Module (AJSM). which provides maximum security to the memory content of the device by allowing users to secure the device after programming.

TMS570LS0232 ajsm_unlock_pns160.gifFigure 6-15 AJSM Unlock

The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.

A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device.

Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.

The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).

A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state.

6.20.7 Boundary Scan Chain

The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module.

TMS570LS0232 boundary_scan_implementation _pns160.gifFigure 6-16 Boundary Scan Implementation (Conceptual Diagram)

Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.