SNVU815 October   2021 LP87564-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Sequencing
  4. 3Register Bits Loaded From OTP Memory

2 Sequencing

Figure 2-1 shows the generic power up and power down timing diagram. Startup delay is the delay from the rising edge of ENABLE signal. Shutdown delay is the delay from the falling edge of ENABLE signal. Note that the ENABLE pin assignment/control method and exact power up and power down sequencing depends on the timing values defined in the OTP and specified in Table 2-1.

Figure 2-1 Generic Startup and Shutdown Sequences of the Regulators
Table 2-1 Startup and Shutdown Sequencing for LP87564T-Q1
BUCK0 BUCK1 BUCK2 BUCK3
Control EN_BUCK0 bit EN_BUCK1 bit EN1 pin EN_BUCK3 bit
Startup delay 0 ms 0 ms 0 ms 0 ms
Shutdown delay 0 ms 0 ms 0 ms 0 ms