SNVSB03D December   2018  – January 2020

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      TPS3840 Typical Supply Current
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Application Curve: TPS3840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

Typical characteristics show the typical performance of the TPS3840 device. Test conditions are TJ = 25°C, VDD = 3.3 V, Rpull-up = 100 kΩ, CLoad = 50 pF, unless otherwise noted.
TPS3840 IDDvsVDD_DL49.gifFigure 7. Supply Current vs Supply Voltage for TPS3840DL49
TPS3840 IDDvsVDD_PH49.gifFigure 9. Supply Current vs Supply Voltage for TPS3840PH49
TPS3840 VIT_accuracy_PL.gifFigure 11. Negative-going Input Threshold Accuracy over Temperature for TPS3840PLXX
TPS3840 Vhys_acc_vs_temp_DL.gifFigure 13. Input Threshold VIT- Hysteresis Accuracy for TPS3840DLXX
TPS3840 Vhys_acc_vs_temp_PH.gifFigure 15. Input Threshold VIT- Hysteresis Accuracy for TPS3840PHXX
TPS3840 VRESET_VDD_PL.gifFigure 17. Output Voltage vs Input Voltage for TPS3840PL49
TPS3840 VOL_IRESET_DL.gifFigure 19. Low Level Output Voltage vs IRESET for TPS3840DL49
TPS3840 VOL_IRESET_PL.gifFigure 21. Low Level Output Voltage vs IRESET for TPS3840PL49
TPS3840 VOL_IRESET_PH.gifFigure 23. Low Level Output Voltage vs IRESET for TPS3840PH49
TPS3840 VOH_IRESET_PL.gifFigure 25. High Level Output Voltage vs IRESET for TPS3840PL49
TPS3840 VOH_IRESET_PH.gifFigure 27. High Level Output Voltage vs IRESET for TPS3840PH49
TPS3840 MR_L_DL.gifFigure 29. Manual Reset Logic Low Voltage Threshold over Temperature for TPS3840DLXX
TPS3840 MR_L_PH.gifFigure 31. Manual Reset Logic Low Voltage Threshold over Temperature for TPS3840PHXX
TPS3840 MR_H_PL.gifFigure 33. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840PLXX
TPS3840 GlitchimmunityPL28.gifFigure 35. Glitch Immunity on VIT- vs Overdrive (Data Taken with TPS3840PL28)
TPS3840 Startuptime.gifFigure 37. Startup Delay over Temperature
TPS3840 Delaywithcap.gifFigure 39. Reset Time Delay vs Capacitor Value (Data Taken with TPS3840PL16)
TPS3840 Delaywithcap_large.gifFigure 41. Reset Time Delay vs Large Capacitor Values (Data Taken with TPS3840PL16)
TPS3840 MR_res.gifFigure 43. Propagation Time Delay from MR Asserted to Reset over Temperature
TPS3840 IDDvsVDD_PL49_smooth.gifFigure 8. Supply Current vs Supply Voltage for TPS3840PL49
TPS3840 VIT_accuracy_DL.gifFigure 10. Negative-going Input Threshold Accuracy over Temperature for TPS3840DLXX
TPS3840 VIT_accuracy_PH.gifFigure 12. Negative-going Input Threshold Accuracy over Temperature for TPS3840PHXX
TPS3840 Vhys_acc_vs_temp_PL.gifFigure 14. Input Threshold VIT- Hysteresis Accuracy for TPS3840PLXX
TPS3840 VRESET_VDD_DL.gifFigure 16. Output Voltage vs Input Voltage for TPS3840DL49
TPS3840 VRESET_VDD_PH.gifFigure 18. Output Voltage vs Input Voltage for TPS3840PH49
TPS3840 VOLvsVDD_DL49.gifFigure 20. Low Level Output Voltage vs VDD for TPS3840DL49
TPS3840 VOLvsVDD_PL49.gifFigure 22. Low Level Output Voltage vs VDD for TPS3840PL49
TPS3840 VOLvsVDD_PH49.gifFigure 24. Low Level Output Voltage vs VDD for TPS3840PH49
TPS3840 VOHvsVDD_PL49.gifFigure 26. High Level Output Voltage over Temperature for TPS3840PL49
TPS3840 VOHvsVDD_PH49.gifFigure 28. High Level Output Voltage over Temperature for TPS3840PH49
TPS3840 MR_L_PL.gifFigure 30. Manual Reset Logic Low Voltage Threshold over Temperature for TPS3840PLXX
TPS3840 MR_H_DL.gifFigure 32. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840DLXX
TPS3840 MR_H_PH.gifFigure 34. Manual Reset Logic High Voltage Threshold over Temperature for TPS3840PHXX
TPS3840 RCTvsTemp.gifFigure 36. CT Pin Internal Resistance over Temperature
TPS3840 DelayTimenocap.gifFigure 38. Reset Time Delay with No Capacitor over Temperature
TPS3840 Delaywithcap_small.gifFigure 40. Reset Time Delay vs Small Capacitor Values (Data Taken with TPS3840PL16)
TPS3840 TPHL.gifFigure 42. Propagation Detect Time Delay for VDD Falling Below VIT- (High-to-Low) over Temperature
TPS3840 MRdeassert.gifFigure 44. Propagation Time Delay from MR Release to Deasserted Reset over Temperature