SNOSD81B September   2018  – January 2020

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Block Diagram
      2.      Switching Performance at >100 V/ns
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-on Delays
      2. 7.1.2 Turn-off Delays
      3. 7.1.3 Drain Slew Rate
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Direct-Drive GaN Architecture
      2. 8.3.2 Internal Buck-Boost DC-DC Converter
      3. 8.3.3 Internal Auxiliary LDO
      4. 8.3.4 Start Up Sequence
      5. 8.3.5 R-C Decoupling for IN pin
      6. 8.3.6 Low Power Mode
      7. 8.3.7 Fault Detection
        1. 8.3.7.1 Over-current Protection
        2. 8.3.7.2 Over-Temperature Protection and UVLO
      8. 8.3.8 Drive Strength Adjustment
    4. 8.4 Safe Operation Area (SOA)
      1. 8.4.1 Repetitive SOA
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Startup and Slew Rate with Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Using an Isolated Power Supply
    2. 10.2 Using a Bootstrap Diode
      1. 10.2.1 Diode Selection
      2. 10.2.2 Managing the Bootstrap Voltage
      3. 10.2.3 Reliable Bootstrap Start-up
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Loop Inductance
      2. 11.1.2 Signal Ground Connection
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Switch-Node Capacitance
      5. 11.1.5 Signal Integrity
      6. 11.1.6 High-Voltage Spacing
      7. 11.1.7 Thermal Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Signal Level-Shifting

As the LMG341xR050 is a single-channel power stage, two devices are used to construct a half-bridge converter, such as the one shown in Figure 21. A high-voltage level shifter or digital isolator must be used to provide signals to the high-side device. Using an isolator for the low-side device is optional but will equalize propagation delays between the high-side and low-side signal path, as well as providing the ability to use different grounds for the power stage and the controller. If an isolator is not used on the low-side device, the control ground and the power ground must be connected at the LMG341xR050, as described in Layout Guidelines, and nowhere else on the board. With the high current slew rate of the fast-switching GaN device, any ground-plane inductance common with the power path may cause oscillation or instability in the power stage without the use of an isolator.

Choosing a digital isolator for level-shifting is an important consideration for fault-free operation. Because GaN switches very quickly, exceeding 50 V/ns in hard-switching applications, isolators with high common-mode transient immunity (CMTI) are required. If an isolator suffers from a CMTI issue, it can output a false pulse or signal which can cause shoot-through. In addition, choosing an isolator that is not edge-triggered can improve circuit robustness. In an edge-triggered isolator, a high dv/dt event can cause the isolator to flip states and cause circuit malfunctioning.

On or off keyed isolators are preferred, such as the TI ISO78xxF series, as a high CMTI event would only cause a short (few nanosecond) false pulse, which can be filtered out. To allow for filtering of these false pulses, an R-C filter at the driver input is recommended to ensure these false pulses can be filtered. If issues are observed, values of 1 kΩ and 22 pF can be used to filter out any false pulses.