SLVUCL9
june 2023
TPS65219
1
ABSTRACT
Trademarks
1
Introduction
2
EEPROM Device Settings
2.1
PDN and Sequence Diagrams
2.1.1
TPS6521907 Sequence and Power Block Diagram
2.2
Device ID
2.3
Enable Settings
2.4
Regulator Voltage Settings
2.5
Power-Up Sequence Settings
2.6
Power-Down Sequence Settings
2.7
EN / PB / VSENSE Settings
2.8
Multi-Function Pin Settings
2.9
Over-Current Deglitch
2.10
Mask Settings
2.11
Discharge Check
2.12
Multi PMIC Config
2.1.1
TPS6521907 Sequence and Power Block Diagram
Figure 2-1
TPS6521907 Example Power Block Diagram
Figure 2-2
TPS6521907 Power-Up Sequence
Figure 2-3
TPS6521907 Power-Down Sequence