This Technical Reference Manual (TRM) can be used as a reference for the default register bits after the NVM download. The end user is responsible for validating the NVM settings for proper system use including any safety impact. This TRM does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the device data sheet available on the TPS65220 product folder at ti.com.
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The TPS65219/TPS65220 PMIC is a cost and space optimized solution that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 Buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C, GPIOs and configurable multi-function pins. TPS65219 is characterized for -40°C to +105°C ambient temperature and TPS65220 is characterized for -40°C to +125°C ambient temperature. The extended PMIC temperature range of TPS65220 allows support of AM64x based systems operating at higher temperatures. For safety sensitive applications, TPS65220 is functional safety capable. Therefore the TPS65220 development process is a TI-quality managed process, also functional safety FIT rate calculation and Failure mode distribution (FMD) is available for TPS65220. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6522053.
A hardware solution is readily available with the AM64x SK EVM Revision 2 using TPS65220 PMIC (SK-AM64B)
The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.
This section lists all the register settings to identify the supported temperature and the NVM ID with the corresponding revision that represent a list of default register settings.
Register Name | Field Name | Value | Description |
---|---|---|---|
TI_DEV_ID | TI_DEVICE_ID | 0x80 | Device specific ID code to identify supported ambient and junction temperature. |
NVM_ID | TI_NVM_ID | 0x53 | Identification code for the NVM ID |
FACTORY_CONFIG_2 | NVM_REVISION | 0x2 | Identification code for the NVM revision |
I2C_ADDRESS_REG | I2C_ADDRESS | 0x30 | I2C address |
This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available.
PMIC Rail | Register Name | Field Name | Value | Description |
---|---|---|---|---|
BUCK1 | ENABLE_CTRL | BUCK1_EN | 0x1 | Enabled |
BUCK2 | ENABLE_CTRL | BUCK2_EN | 0x1 | Enabled |
BUCK3 | ENABLE_CTRL | BUCK3_EN | 0x1 | Enabled |
LDO1 | ENABLE_CTRL | LDO1_EN | 0x1 | Enabled |
LDO2 | ENABLE_CTRL | LDO2_EN | 0x1 | Enabled |
LDO3 | ENABLE_CTRL | LDO3_EN | 0x1 | Enabled |
LDO4 | ENABLE_CTRL | LDO4_EN | 0x1 | Enabled |
GPO1 | GENERAL_CONFIG | GPO1_EN | 0x0 | The GPO1 function is disabled. The output state is low. |
GPO2 | GENERAL_CONFIG | GPO2_EN | 0x1 | The GPO2 function is enabled. The output state is Hi-Z. |
GPIO | GENERAL_CONFIG | GPIO_EN | 0x0 | The GPIO function is disabled. The output state is low. |
PMIC Rail | Register Name | Field Name | Value | Description |
---|---|---|---|---|
BUCK1 | STBY_1_CONFIG | BUCK1_STBY_EN | 0x1 | Enabled in STBY Mode |
BUCK2 | STBY_1_CONFIG | BUCK2_STBY_EN | 0x1 | Enabled in STBY Mode |
BUCK3 | STBY_1_CONFIG | BUCK3_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO1 | STBY_1_CONFIG | LDO1_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO2 | STBY_1_CONFIG | LDO2_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO3 | STBY_1_CONFIG | LDO3_STBY_EN | 0x1 | Enabled in STBY Mode |
LDO4 | STBY_1_CONFIG | LDO4_STBY_EN | 0x1 | Enabled in STBY Mode |
GPO1 | STBY_2_CONFIG | GPO1_STBY_EN | 0x0 | Disabled in STBY Mode |
GPO2 | STBY_2_CONFIG | GPO2_STBY_EN | 0x1 | Enabled in STBY Mode |
GPIO | STBY_2_CONFIG | GPIO_STBY_EN | 0x0 | Disabled in STBY Mode |
This section describes how each of the PMIC power resources were configured.
PMIC Rail | Register Name | Field Name | Value | Description |
---|---|---|---|---|
Bucks Switching Mode (Global for all Buck regulators) |
BUCKS_CONFIG | BUCK_FF_ENABLE | 0x0 | Quasi-fixed frequency mode |
BUCKS_CONFIG | BUCK_SS_ENABLE | 0x0 | Spread spectrum disabled | |
BUCK1 | BUCK1_VOUT | BUCK1_VSET | 0x6 | 0.750V |
BUCK1_VOUT | BUCK1_UV_THR_SEL | 0x0 | -5% UV detection level | |
BUCK1_VOUT | BUCK1_BW_SEL | 0x1 | high bandwidth | |
BUCK2 | BUCK2_VOUT | BUCK2_VSET | 0x24 | 1.800V |
BUCK2_VOUT | BUCK2_UV_THR_SEL | 0x0 | -5% UV detection level | |
BUCK2_VOUT | BUCK2_BW_SEL | 0x1 | high bandwidth | |
BUCKS_CONFIG | BUCK2_PHASE_CONFIG | 0x3 | 270 degrees (only applicable if Bucks are configured for fixed frequency) | |
BUCK3 | BUCK3_VOUT | BUCK3_VSET | 0x14 | 1.100V |
BUCK3_VOUT | BUCK3_UV_THR_SEL | 0x0 | -5% UV detection level | |
BUCK3_VOUT | BUCK3_BW_SEL | 0x1 | high bandwidth | |
BUCKS_CONFIG | BUCK3_PHASE_CONFIG | 0x2 | 180 degrees (only applicable if Bucks are configured for fixed frequency) |
PMIC Rail | Setting | Register Name | Field Name | Value | Description |
---|---|---|---|---|---|
LDO1 | LDO1 output voltage | LDO1_VOUT | LDO1_VSET | 0x36 | 3.300V |
LDO1 configuration | LDO1_VOUT | LDO1_LSW_CONFIG | 0x0 | Not Applicable (LDO1 not configured as load-switch) | |
LDO1_VOUT | LDO1_BYP_CONFIG | 0x1 | LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG=0x0) | ||
LDO1 UV threshold | GENERAL_CONFIG | LDO1_UV_THR | 0x0 | -5% UV detection level (only applicable if configured as LDO) | |
LDO2 | LDO2 output voltage | LDO2_VOUT | LDO2_VSET | 0x5 | 0.850V / reserved |
LDO2 configuration | LDO2_VOUT | LDO2_LSW_CONFIG | 0x0 | Not Applicable (LDO2 not configured as load-switch) | |
LDO2_VOUT | LDO2_BYP_CONFIG | 0x0 | LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG=0x0) | ||
LDO2 UV threshold | GENERAL_CONFIG | LDO2_UV_THR | 0x0 | -5% UV detection level (only applicable if configured as LDO) | |
LDO3 | LDO3 output voltage | LDO3_VOUT | LDO3_VSET | 0x18 | 1.800V |
LDO3 configuration | LDO3_VOUT | LDO3_LSW_CONFIG | 0x0 | LDO Mode | |
LDO ramp configuration | LDO3_VOUT | LDO3_SLOW_PU_RAMP | 0x1 | Slow ramp for power-up (~3ms) | |
LDO3 UV threshold | GENERAL_CONFIG | LDO3_UV_THR | 0x0 | -5% UV detection level (only applicable if configured as LDO) | |
LDO4 | LDO4 output voltage | LDO4_VOUT | LDO4_VSET | 0x26 | 2.500V |
LDO3 configuration | LDO4_VOUT | LDO4_LSW_CONFIG | 0x0 | LDO Mode | |
LDO ramp configuration | LDO4_VOUT | LDO4_SLOW_PU_RAMP | 0x1 | Slow ramp for power-up (~3ms) | |
LDO4 UV threshold | GENERAL_CONFIG | LDO4_UV_THR | 0x0 | -5% UV detection level (only applicable if configured as LDO) |
This section breaks out the power sequence settings for the device including the power-up/power-down slot assignment and duration. There may be slots in which no rail nor GPO is assigned to ramp. In this case, we use a combination of slot durations to achieve desired delay times or allow to increase/reduce the timings.
Register Name | Field Name | Value | Description | |
---|---|---|---|---|
BUCK1 | BUCK1_SEQUENCE_SLOT | BUCK1_SEQUENCE_ON_SLOT | 0x4 | slot 4 |
BUCK2 | BUCK2_SEQUENCE_SLOT | BUCK2_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
BUCK3 | BUCK3_SEQUENCE_SLOT | BUCK3_SEQUENCE_ON_SLOT | 0x3 | slot 3 |
LDO1 | LDO1_SEQUENCE_SLOT | LDO1_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
LDO2 | LDO2_SEQUENCE_SLOT | LDO2_SEQUENCE_ON_SLOT | 0x5 | slot 5 |
LDO3 | LDO3_SEQUENCE_SLOT | LDO3_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
LDO4 | LDO4_SEQUENCE_SLOT | LDO4_SEQUENCE_ON_SLOT | 0x2 | slot 2 |
GPO1 | GPO1_SEQUENCE_SLOT | GPO1_SEQUENCE_ON_SLOT | 0x6 | slot 6 |
GPO2 | GPO2_SEQUENCE_SLOT | GPO2_SEQUENCE_ON_SLOT | 0x0 | slot 0 |
GPIO | GPIO_SEQUENCE_SLOT | GPIO_SEQUENCE_ON_SLOT | 0x6 | slot 6 |
nRSTOUT | nRST_SEQUENCE_SLOT | nRST_SEQUENCE_ON_SLOT | 0x8 | slot 8 |
Register Name | Field Name | Value | Description | |
---|---|---|---|---|
BUCK1 | BUCK1_SEQUENCE_SLOT | BUCK1_SEQUENCE_OFF_SLOT | 0x1 | slot 1 |
BUCK2 | BUCK2_SEQUENCE_SLOT | BUCK2_SEQUENCE_OFF_SLOT | 0x1 | slot 1 |
BUCK3 | BUCK3_SEQUENCE_SLOT | BUCK3_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
LDO1 | LDO1_SEQUENCE_SLOT | LDO1_SEQUENCE_OFF_SLOT | 0x1 | slot 1 |
LDO2 | LDO2_SEQUENCE_SLOT | LDO2_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
LDO3 | LDO3_SEQUENCE_SLOT | LDO3_SEQUENCE_OFF_SLOT | 0x1 | slot 1 |
LDO4 | LDO4_SEQUENCE_SLOT | LDO4_SEQUENCE_OFF_SLOT | 0x1 | slot 1 |
GPO1 | GPO1_SEQUENCE_SLOT | GPO1_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
GPO2 | GPO2_SEQUENCE_SLOT | GPO2_SEQUENCE_OFF_SLOT | 0x2 | slot 2 |
GPIO | GPIO_SEQUENCE_SLOT | GPIO_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
nRSTOUT | nRST_SEQUENCE_SLOT | nRST_SEQUENCE_OFF_SLOT | 0x0 | slot 0 |
Register Name | Field Name | Value | Description | |
---|---|---|---|---|
SLOT0 | POWER_UP_SLOT_DURATION_1 | POWER_UP_SLOT_0_DURATION | 0x2 | 3ms |
SLOT1 | POWER_UP_SLOT_DURATION_1 | POWER_UP_SLOT_1_DURATION | 0x2 | 3ms |
SLOT2 | POWER_UP_SLOT_DURATION_1 | POWER_UP_SLOT_2_DURATION | 0x2 | 3ms |
SLOT3 | POWER_UP_SLOT_DURATION_1 | POWER_UP_SLOT_3_DURATION | 0x1 | 1.5ms |
SLOT4 | POWER_UP_SLOT_DURATION_2 | POWER_UP_SLOT_4_DURATION | 0x1 | 1.5ms |
SLOT5 | POWER_UP_SLOT_DURATION_2 | POWER_UP_SLOT_5_DURATION | 0x1 | 1.5ms |
SLOT6 | POWER_UP_SLOT_DURATION_2 | POWER_UP_SLOT_6_DURATION | 0x3 | 10ms |
SLOT7 | POWER_UP_SLOT_DURATION_2 | POWER_UP_SLOT_7_DURATION | 0x1 | 1.5ms |
SLOT8 | POWER_UP_SLOT_DURATION_3 | POWER_UP_SLOT_8_DURATION | 0x3 | 10ms |
SLOT9 | POWER_UP_SLOT_DURATION_3 | POWER_UP_SLOT_9_DURATION | 0x0 | 0ms |
SLOT10 | POWER_UP_SLOT_DURATION_3 | POWER_UP_SLOT_10_DURATION | 0x0 | 0ms |
SLOT11 | POWER_UP_SLOT_DURATION_3 | POWER_UP_SLOT_11_DURATION | 0x0 | 0ms |
SLOT12 | POWER_UP_SLOT_DURATION_4 | POWER_UP_SLOT_12_DURATION | 0x0 | 0ms |
SLOT13 | POWER_UP_SLOT_DURATION_4 | POWER_UP_SLOT_13_DURATION | 0x0 | 0ms |
SLOT14 | POWER_UP_SLOT_DURATION_4 | POWER_UP_SLOT_14_DURATION | 0x0 | 0ms |
SLOT15 | POWER_UP_SLOT_DURATION_4 | POWER_UP_SLOT_15_DURATION | 0x0 | 0ms |
Register Name | Field Name | Value | Description | |
---|---|---|---|---|
SLOT0 | POWER_DOWN_SLOT_DURATION_1 | POWER_DOWN_SLOT_0_DURATION | 0x3 | 10ms |
SLOT1 | POWER_DOWN_SLOT_DURATION_1 | POWER_DOWN_SLOT_1_DURATION | 0x3 | 10ms |
SLOT2 | POWER_DOWN_SLOT_DURATION_1 | POWER_DOWN_SLOT_2_DURATION | 0x0 | 0ms |
SLOT3 | POWER_DOWN_SLOT_DURATION_1 | POWER_DOWN_SLOT_3_DURATION | 0x0 | 0ms |
SLOT4 | POWER_DOWN_SLOT_DURATION_2 | POWER_DOWN_SLOT_4_DURATION | 0x0 | 0ms |
SLOT5 | POWER_DOWN_SLOT_DURATION_2 | POWER_DOWN_SLOT_5_DURATION | 0x0 | 0ms |
SLOT6 | POWER_DOWN_SLOT_DURATION_2 | POWER_DOWN_SLOT_6_DURATION | 0x0 | 0ms |
SLOT7 | POWER_DOWN_SLOT_DURATION_2 | POWER_DOWN_SLOT_7_DURATION | 0x0 | 0ms |
SLOT8 | POWER_DOWN_SLOT_DURATION_3 | POWER_DOWN_SLOT_8_DURATION | 0x0 | 0ms |
SLOT9 | POWER_DOWN_SLOT_DURATION_3 | POWER_DOWN_SLOT_9_DURATION | 0x0 | 0ms |
SLOT10 | POWER_DOWN_SLOT_DURATION_3 | POWER_DOWN_SLOT_10_DURATION | 0x0 | 0ms |
SLOT11 | POWER_DOWN_SLOT_DURATION_3 | POWER_DOWN_SLOT_11_DURATION | 0x0 | 0ms |
SLOT12 | POWER_DOWN_SLOT_DURATION_4 | POWER_DOWN_SLOT_12_DURATION | 0x0 | 0ms |
SLOT13 | POWER_DOWN_SLOT_DURATION_4 | POWER_DOWN_SLOT_13_DURATION | 0x0 | 0ms |
SLOT14 | POWER_DOWN_SLOT_DURATION_4 | POWER_DOWN_SLOT_14_DURATION | 0x0 | 0ms |
SLOT15 | POWER_DOWN_SLOT_DURATION_4 | POWER_DOWN_SLOT_15_DURATION | 0x0 | 0ms |