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  • TPS6522053 Technical Reference Manual

    • SLVUCJ3 February   2023 TPS65220

       

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  • TPS6522053 Technical Reference Manual
  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  5. IMPORTANT NOTICE
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TECHNICAL REFERENCE

TPS6522053 Technical Reference Manual

1 ABSTRACT

This Technical Reference Manual (TRM) can be used as a reference for the default register bits after the NVM download. The end user is responsible for validating the NVM settings for proper system use including any safety impact. This TRM does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the device data sheet available on the TPS65220 product folder at ti.com.

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

The TPS65219/TPS65220 PMIC is a cost and space optimized solution that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 Buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C, GPIOs and configurable multi-function pins. TPS65219 is characterized for -40°C to +105°C ambient temperature and TPS65220 is characterized for -40°C to +125°C ambient temperature. The extended PMIC temperature range of TPS65220 allows support of AM64x based systems operating at higher temperatures. For safety sensitive applications, TPS65220 is functional safety capable. Therefore the TPS65220 development process is a TI-quality managed process, also functional safety FIT rate calculation and Failure mode distribution (FMD) is available for TPS65220. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6522053.

A hardware solution is readily available with the AM64x SK EVM Revision 2 using TPS65220 PMIC (SK-AM64B)

Note: The NVM configuration described in this document is ideal for the application described below but can also be used to power other processors or SoCs with equivalent power requirements:

  • Processor: AM62, AM64
  • CORE voltage: 0.75V
  • Memory: LPDDR4
  • Input Supply (VSYS, PVIN_Bx): 3.3V

2 EEPROM Device Settings

The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.

2.1 Device ID

This section lists all the register settings to identify the supported temperature and the NVM ID with the corresponding revision that represent a list of default register settings.

Table 2-1 Device ID
Register Name Field Name Value Description
TI_DEV_ID TI_DEVICE_ID 0x80 Device specific ID code to identify supported ambient and junction temperature.
NVM_ID TI_NVM_ID 0x53 Identification code for the NVM ID
FACTORY_CONFIG_2 NVM_REVISION 0x2 Identification code for the NVM revision
I2C_ADDRESS_REG I2C_ADDRESS 0x30 I2C address

 

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