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  • TPS6522053 Technical Reference Manual

    • SLVUCJ3 February   2023 TPS65220

       

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  • TPS6522053 Technical Reference Manual
  1.   ABSTRACT
  2.   Trademarks
  3. 1Introduction
  4. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6522053 Sequence and Power Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  5. IMPORTANT NOTICE
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TECHNICAL REFERENCE

TPS6522053 Technical Reference Manual

1 ABSTRACT

This Technical Reference Manual (TRM) can be used as a reference for the default register bits after the NVM download. The end user is responsible for validating the NVM settings for proper system use including any safety impact. This TRM does not provide information about the electrical characteristics, external components, package, or the functionality of the device. For this information and the full register map, refer to the device data sheet available on the TPS65220 product folder at ti.com.

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

The TPS65219/TPS65220 PMIC is a cost and space optimized solution that has flexible mapping to support the power requirements from different processors and SoCs. This PMIC contains seven regulators; 3 Buck regulators and 4 Low Drop-out Regulators (LDOs). Additionally, it has I2C, GPIOs and configurable multi-function pins. TPS65219 is characterized for -40°C to +105°C ambient temperature and TPS65220 is characterized for -40°C to +125°C ambient temperature. The extended PMIC temperature range of TPS65220 allows support of AM64x based systems operating at higher temperatures. For safety sensitive applications, TPS65220 is functional safety capable. Therefore the TPS65220 development process is a TI-quality managed process, also functional safety FIT rate calculation and Failure mode distribution (FMD) is available for TPS65220. Whenever entering the INITIALIZE state, the PMIC reads its memory and loads the registers with the content from the EEPROM. The EEPROM loading takes approximately 2.3ms. The power-up sequence can only be executed after the EEPROM-load and all rails are discharged below the SCG threshold. This document describes the default configuration programmed on TPS6522053.

A hardware solution is readily available with the AM64x SK EVM Revision 2 using TPS65220 PMIC (SK-AM64B)

Note: The NVM configuration described in this document is ideal for the application described below but can also be used to power other processors or SoCs with equivalent power requirements:

  • Processor: AM62, AM64
  • CORE voltage: 0.75V
  • Memory: LPDDR4
  • Input Supply (VSYS, PVIN_Bx): 3.3V

2 EEPROM Device Settings

The following sections describe the default configuration on the EEPROM-backed registers. During the power-down-sequence, non-EEPROM-backed bits get reset, with the exception of unmasked interrupt bits and DISCHARGE_EN bits.

2.1 Device ID

This section lists all the register settings to identify the supported temperature and the NVM ID with the corresponding revision that represent a list of default register settings.

Table 2-1 Device ID
Register Name Field Name Value Description
TI_DEV_ID TI_DEVICE_ID 0x80 Device specific ID code to identify supported ambient and junction temperature.
NVM_ID TI_NVM_ID 0x53 Identification code for the NVM ID
FACTORY_CONFIG_2 NVM_REVISION 0x2 Identification code for the NVM revision
I2C_ADDRESS_REG I2C_ADDRESS 0x30 I2C address

2.2 Enable Settings

This section describes the PMIC rails that are enabled in Active and Standby state. Any rail that is disabled by default has the option to be enabled through I2C once the device is in Active state and I2C communication is available.

Table 2-2 Enable Settings - ACTIVE state
PMIC Rail Register Name Field Name Value Description
BUCK1 ENABLE_CTRL BUCK1_EN 0x1 Enabled
BUCK2 ENABLE_CTRL BUCK2_EN 0x1 Enabled
BUCK3 ENABLE_CTRL BUCK3_EN 0x1 Enabled
LDO1 ENABLE_CTRL LDO1_EN 0x1 Enabled
LDO2 ENABLE_CTRL LDO2_EN 0x1 Enabled
LDO3 ENABLE_CTRL LDO3_EN 0x1 Enabled
LDO4 ENABLE_CTRL LDO4_EN 0x1 Enabled
GPO1 GENERAL_CONFIG GPO1_EN 0x0 The GPO1 function is disabled. The output state is low.
GPO2 GENERAL_CONFIG GPO2_EN 0x1 The GPO2 function is enabled. The output state is Hi-Z.
GPIO GENERAL_CONFIG GPIO_EN 0x0 The GPIO function is disabled. The output state is low.
Table 2-3 Enable Settings - STANBY (STBY) state
PMIC Rail Register Name Field Name Value Description
BUCK1 STBY_1_CONFIG BUCK1_STBY_EN 0x1 Enabled in STBY Mode
BUCK2 STBY_1_CONFIG BUCK2_STBY_EN 0x1 Enabled in STBY Mode
BUCK3 STBY_1_CONFIG BUCK3_STBY_EN 0x1 Enabled in STBY Mode
LDO1 STBY_1_CONFIG LDO1_STBY_EN 0x1 Enabled in STBY Mode
LDO2 STBY_1_CONFIG LDO2_STBY_EN 0x1 Enabled in STBY Mode
LDO3 STBY_1_CONFIG LDO3_STBY_EN 0x1 Enabled in STBY Mode
LDO4 STBY_1_CONFIG LDO4_STBY_EN 0x1 Enabled in STBY Mode
GPO1 STBY_2_CONFIG GPO1_STBY_EN 0x0 Disabled in STBY Mode
GPO2 STBY_2_CONFIG GPO2_STBY_EN 0x1 Enabled in STBY Mode
GPIO STBY_2_CONFIG GPIO_STBY_EN 0x0 Disabled in STBY Mode

2.3 Regulator Voltage Settings

This section describes how each of the PMIC power resources were configured.

Table 2-4 Buck Regulator Settings
PMIC RailRegister NameField NameValueDescription
Bucks Switching Mode

(Global for all Buck regulators)

BUCKS_CONFIG BUCK_FF_ENABLE 0x0 Quasi-fixed frequency mode
BUCKS_CONFIG BUCK_SS_ENABLE 0x0 Spread spectrum disabled
BUCK1BUCK1_VOUTBUCK1_VSET0x60.750V
BUCK1_VOUT BUCK1_UV_THR_SEL 0x0 -5% UV detection level
BUCK1_VOUT BUCK1_BW_SEL 0x1 high bandwidth
BUCK2BUCK2_VOUT BUCK2_VSET0x241.800V
BUCK2_VOUT BUCK2_UV_THR_SEL 0x0 -5% UV detection level
BUCK2_VOUT BUCK2_BW_SEL 0x1 high bandwidth
BUCKS_CONFIG BUCK2_PHASE_CONFIG 0x3 270 degrees (only applicable if Bucks are configured for fixed frequency)
BUCK3BUCK3_VOUTBUCK3_VSET0x141.100V
BUCK3_VOUT BUCK3_UV_THR_SEL 0x0 -5% UV detection level
BUCK3_VOUT BUCK3_BW_SEL 0x1 high bandwidth
BUCKS_CONFIG BUCK3_PHASE_CONFIG 0x2 180 degrees (only applicable if Bucks are configured for fixed frequency)

Note:
  • When Bucks are configured for quasi-fixed frequency (BUCK_FF_ENABLE=0x0), changing the switching mode between auto-PFM and forced-PWM can be triggered by I2C (MODE_I2C_CTRL) or with one of the multi-function pins (MODE/RESET or MODE/STBY) if one of them is configured as MODE. "Forced PWM" has priority over "Auto PFM".
  • "BUCK2_PHASE_CONFIG", "BUCK3_PHASE_CONFIG" and "BUCK_SS_ENABLE" are only applicable when the Buck regulators are configured for fixed frequency (BUCK_FF_ENABLE=0x1).

Table 2-5 LDO Regulator Settings
PMIC Rail Setting Register Name Field Name Value Description
LDO1 LDO1 output voltage LDO1_VOUT LDO1_VSET 0x36 3.300V
LDO1 configuration LDO1_VOUT LDO1_LSW_CONFIG 0x0 Not Applicable (LDO1 not configured as load-switch)
LDO1_VOUT LDO1_BYP_CONFIG 0x1 LDO1 configured as Bypass (only applicable if LDO1_LSW_CONFIG=0x0)
LDO1 UV threshold GENERAL_CONFIG LDO1_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO2 LDO2 output voltage LDO2_VOUT LDO2_VSET 0x5 0.850V / reserved
LDO2 configuration LDO2_VOUT LDO2_LSW_CONFIG 0x0 Not Applicable (LDO2 not configured as load-switch)
LDO2_VOUT LDO2_BYP_CONFIG 0x0 LDO2 configured as LDO (only applicable if LDO2_LSW_CONFIG=0x0)
LDO2 UV threshold GENERAL_CONFIG LDO2_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO3 LDO3 output voltage LDO3_VOUT LDO3_VSET 0x18 1.800V
LDO3 configuration LDO3_VOUT LDO3_LSW_CONFIG 0x0 LDO Mode
LDO ramp configuration LDO3_VOUT LDO3_SLOW_PU_RAMP 0x1 Slow ramp for power-up (~3ms)
LDO3 UV threshold GENERAL_CONFIG LDO3_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
LDO4 LDO4 output voltage LDO4_VOUT LDO4_VSET 0x26 2.500V
LDO3 configuration LDO4_VOUT LDO4_LSW_CONFIG 0x0 LDO Mode
LDO ramp configuration LDO4_VOUT LDO4_SLOW_PU_RAMP 0x1 Slow ramp for power-up (~3ms)
LDO4 UV threshold GENERAL_CONFIG LDO4_UV_THR 0x0 -5% UV detection level (only applicable if configured as LDO)
Note:
  • If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
  • If an LDO is configured in bypass-mode, the corresponding PVIN_LDOx supply must match the configured output voltage in the LDOx_VOUT register.
  • If LDO is configured as load-switch (LSW_mode), the desired voltage does not need to be configured in the LDOx_VOUT register.
  • In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the FET-resistance.
  • If LDO1 or LDO2 is configured as bypass, it allows voltage and function changes between LDO (VOUT=1.8V) and VOUT=VSET register setting. This voltage/function change can be triggered by hardware (using the VSEL_SD pin when configured as SD) or by software (VSEL_SD_I2C_CTRL).

2.4 Power Sequence Settings

This section breaks out the power sequence settings for the device including the power-up/power-down slot assignment and duration. There may be slots in which no rail nor GPO is assigned to ramp. In this case, we use a combination of slot durations to achieve desired delay times or allow to increase/reduce the timings.

2.4.1 Power Sequence Settings - Slot assignments

Table 2-6 Power-UP Sequence Settings - Slot Assignments
Register Name Field Name Value Description
BUCK1 BUCK1_SEQUENCE_SLOT BUCK1_SEQUENCE_ON_SLOT 0x4 slot 4
BUCK2 BUCK2_SEQUENCE_SLOT BUCK2_SEQUENCE_ON_SLOT 0x2 slot 2
BUCK3 BUCK3_SEQUENCE_SLOT BUCK3_SEQUENCE_ON_SLOT 0x3 slot 3
LDO1 LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_ON_SLOT 0x2 slot 2
LDO2 LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_ON_SLOT 0x5 slot 5
LDO3 LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_ON_SLOT 0x2 slot 2
LDO4 LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_ON_SLOT 0x2 slot 2
GPO1 GPO1_SEQUENCE_SLOT GPO1_SEQUENCE_ON_SLOT 0x6 slot 6
GPO2 GPO2_SEQUENCE_SLOT GPO2_SEQUENCE_ON_SLOT 0x0 slot 0
GPIO GPIO_SEQUENCE_SLOT GPIO_SEQUENCE_ON_SLOT 0x6 slot 6
nRSTOUT nRST_SEQUENCE_SLOT nRST_SEQUENCE_ON_SLOT 0x8 slot 8

Note: PMIC rails are turned ON during the power-up sequence if the corresponding EN bit on section "Enable Setting" is set to 0x01.

Table 2-7 Power-Down Sequence Settings - Slot Assignments
Register Name Field Name Value Description
BUCK1 BUCK1_SEQUENCE_SLOT BUCK1_SEQUENCE_OFF_SLOT 0x1 slot 1
BUCK2 BUCK2_SEQUENCE_SLOT BUCK2_SEQUENCE_OFF_SLOT 0x1 slot 1
BUCK3 BUCK3_SEQUENCE_SLOT BUCK3_SEQUENCE_OFF_SLOT 0x0 slot 0
LDO1 LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_OFF_SLOT 0x1 slot 1
LDO2 LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_OFF_SLOT 0x0 slot 0
LDO3 LDO3_SEQUENCE_SLOT LDO3_SEQUENCE_OFF_SLOT 0x1 slot 1
LDO4 LDO4_SEQUENCE_SLOT LDO4_SEQUENCE_OFF_SLOT 0x1 slot 1
GPO1 GPO1_SEQUENCE_SLOT GPO1_SEQUENCE_OFF_SLOT 0x0 slot 0
GPO2 GPO2_SEQUENCE_SLOT GPO2_SEQUENCE_OFF_SLOT 0x2 slot 2
GPIO GPIO_SEQUENCE_SLOT GPIO_SEQUENCE_OFF_SLOT 0x0 slot 0
nRSTOUT nRST_SEQUENCE_SLOT nRST_SEQUENCE_OFF_SLOT 0x0 slot 0

2.4.2 Power Sequence Settings - Slot Durations

Table 2-8 Power Sequence Settings - Power-UP Slot Durations
Register Name Field Name Value Description
SLOT0 POWER_UP_SLOT_DURATION_1 POWER_UP_SLOT_0_DURATION 0x2 3ms
SLOT1 POWER_UP_SLOT_DURATION_1 POWER_UP_SLOT_1_DURATION 0x2 3ms
SLOT2 POWER_UP_SLOT_DURATION_1 POWER_UP_SLOT_2_DURATION 0x2 3ms
SLOT3 POWER_UP_SLOT_DURATION_1 POWER_UP_SLOT_3_DURATION 0x1 1.5ms
SLOT4 POWER_UP_SLOT_DURATION_2 POWER_UP_SLOT_4_DURATION 0x1 1.5ms
SLOT5 POWER_UP_SLOT_DURATION_2 POWER_UP_SLOT_5_DURATION 0x1 1.5ms
SLOT6 POWER_UP_SLOT_DURATION_2 POWER_UP_SLOT_6_DURATION 0x3 10ms
SLOT7 POWER_UP_SLOT_DURATION_2 POWER_UP_SLOT_7_DURATION 0x1 1.5ms
SLOT8 POWER_UP_SLOT_DURATION_3 POWER_UP_SLOT_8_DURATION 0x3 10ms
SLOT9 POWER_UP_SLOT_DURATION_3 POWER_UP_SLOT_9_DURATION 0x0 0ms
SLOT10 POWER_UP_SLOT_DURATION_3 POWER_UP_SLOT_10_DURATION 0x0 0ms
SLOT11 POWER_UP_SLOT_DURATION_3 POWER_UP_SLOT_11_DURATION 0x0 0ms
SLOT12 POWER_UP_SLOT_DURATION_4 POWER_UP_SLOT_12_DURATION 0x0 0ms
SLOT13 POWER_UP_SLOT_DURATION_4 POWER_UP_SLOT_13_DURATION 0x0 0ms
SLOT14 POWER_UP_SLOT_DURATION_4 POWER_UP_SLOT_14_DURATION 0x0 0ms
SLOT15 POWER_UP_SLOT_DURATION_4 POWER_UP_SLOT_15_DURATION 0x0 0ms
Table 2-9 Power Sequence Settings - Power-Down Slot Durations
Register Name Field Name Value Description
SLOT0 POWER_DOWN_SLOT_DURATION_1 POWER_DOWN_SLOT_0_DURATION 0x3 10ms
SLOT1 POWER_DOWN_SLOT_DURATION_1 POWER_DOWN_SLOT_1_DURATION 0x3 10ms
SLOT2 POWER_DOWN_SLOT_DURATION_1 POWER_DOWN_SLOT_2_DURATION 0x0 0ms
SLOT3 POWER_DOWN_SLOT_DURATION_1 POWER_DOWN_SLOT_3_DURATION 0x0 0ms
SLOT4 POWER_DOWN_SLOT_DURATION_2 POWER_DOWN_SLOT_4_DURATION 0x0 0ms
SLOT5 POWER_DOWN_SLOT_DURATION_2 POWER_DOWN_SLOT_5_DURATION 0x0 0ms
SLOT6 POWER_DOWN_SLOT_DURATION_2 POWER_DOWN_SLOT_6_DURATION 0x0 0ms
SLOT7 POWER_DOWN_SLOT_DURATION_2 POWER_DOWN_SLOT_7_DURATION 0x0 0ms
SLOT8 POWER_DOWN_SLOT_DURATION_3 POWER_DOWN_SLOT_8_DURATION 0x0 0ms
SLOT9 POWER_DOWN_SLOT_DURATION_3 POWER_DOWN_SLOT_9_DURATION 0x0 0ms
SLOT10 POWER_DOWN_SLOT_DURATION_3 POWER_DOWN_SLOT_10_DURATION 0x0 0ms
SLOT11 POWER_DOWN_SLOT_DURATION_3 POWER_DOWN_SLOT_11_DURATION 0x0 0ms
SLOT12 POWER_DOWN_SLOT_DURATION_4 POWER_DOWN_SLOT_12_DURATION 0x0 0ms
SLOT13 POWER_DOWN_SLOT_DURATION_4 POWER_DOWN_SLOT_13_DURATION 0x0 0ms
SLOT14 POWER_DOWN_SLOT_DURATION_4 POWER_DOWN_SLOT_14_DURATION 0x0 0ms
SLOT15 POWER_DOWN_SLOT_DURATION_4 POWER_DOWN_SLOT_15_DURATION 0x0 0ms

2.4.3 TPS6522053 Sequence and Power Block Diagram

Figure 2-1 TPS6522053 Power-Up Sequence
Figure 2-2 TPS6522053 Power-Down Sequence
Figure 2-3 TPS6522053 Example Power Block Diagram

 

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