SLVU938A July   2013  – August 2021 TPS54625

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1  Input/Output Connections
    2. 4.2  Start-Up Procedure
    3. 4.3  Efficiency
    4. 4.4  Load Regulation
    5. 4.5  Line Regulation
    6. 4.6  Load Transient Response
    7. 4.7  Output Voltage Ripple
    8. 4.8  Input Voltage Ripple
    9. 4.9  Start-Up
    10. 4.10 Shut-Down
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 Reference
  8. 7Revision History

Layout

The board layout for the TPS54625EVM-608 is shown in Figure 5-1 through Figure 5-6. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS54625 and a large area filled with ground. Many of the signal traces also are located on the top side. The input decoupling capacitors are located as close to the IC as possible. The input and output connectors, test points, and most of the components are located on the top side. R3, the 0-Ω resistor that connects VIN to VCC and R4, the power good pull up, are located on the back side. Analog ground and power ground are connected at a single point on the top layer near pin 5 of the TPS54625. The internal layer 1 is a split plane containing analog and power grounds. The internal layer 2 is primarily power ground but also has a fill area of VIN and a trace routing VCC to the enable control jumper JP1. The bottom layer is primarily analog ground but also has traces to connect VIN to VCC through R3, traces for the power good signal, and the feedback trace from VOUT to the voltage setpoint divider network.

GUID-5C8B0EC5-7E57-4810-B8CB-016BE892AC46-low.gifFigure 5-1 Top Assembly
GUID-CC0CEAF5-22B1-40D0-95B5-B7EB1D5B9D1F-low.gifFigure 5-2 Top Layer
GUID-62E92CCB-A624-4C04-95B5-7BEF85791EE2-low.gifFigure 5-3 Internal Layer 1
GUID-B79D9148-83F3-4239-B40C-A342D2EB0C68-low.gifFigure 5-4 Internal Layer 2
GUID-40950B8A-B1A1-429D-BF09-2FDB68BD0A5A-low.gifFigure 5-5 Bottom Layer
GUID-82C082F4-BA45-4DA0-9A5C-08DD67652405-low.gifFigure 5-6 Bottom Assembly