SLVU793A October   2012  – June 2021 TPS56921

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Slow-Start Time
      3. 1.3.3 Adjustable UVLO
      4. 1.3.4 Input Voltage Rails
  3. 2Test Setup and Results
    1. 2.1 Input/Output Connections
    2. 2.2 Efficiency
    3. 2.3 Output Voltage Load Regulation
    4. 2.4 Output Voltage Line Regulation
    5. 2.5 Load Transients
    6. 2.6 Loop Characteristics
    7. 2.7 Output Voltage Ripple
    8. 2.8 Input Voltage Ripple
    9. 2.9 Powering Up
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 Input/Output Connections

The TPS56921EVM-188 is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying 4 A must be connected to J2 through a pair of 20-AWG wires. The jumper across JP1 must be in place. See Section 1.3.4 for split-input voltage rail operation. The load must be connected to J4 through a pair of 20-AWG wires. The maximum load current capability must be 9 A. Wire lengths must be minimized to reduce losses in the wires. Test-point TP3 provides a place to monitor the VIN input voltages with TP4 providing a convenient ground reference. TP9 is used to monitor the output voltage with TP10 as the ground reference.

Table 2-1 EVM Connectors and Test Points
Reference DesignatorFunction
J1VIN input voltage connector. Not normally used.
J2PVIN input voltage connector. (See Table 1-1 for VIN range.)
J3I2C interface connector.
J4VOUT, 1.1 V at 9 A maximum
JP1PVIN to VIN jumper. Normally closed to tie VIN to PVIN for common rail voltage operation.
JP22-pin header for enable. Connect EN to ground to disable, open to enable.
JP3I2C interface pull up jumper for SDA.
JP4I2C interface pull up jumper for SCL.
JP5I2C interface grounding jumper for A0.
JP6I2C interface grounding jumper for A1.
JP7PWRGD pull up to Vin. (1)
TP1VIN test point at VIN connector.
TP2GND test point at VIN connector.
TP3PVIN test point at PVIN connector.
TP4GND test point at PVIN connector.
TP5PWRGD test point.
TP6PH test point.
TP7COMP pin test point.
TP8Analog GND test point.
TP9Test point in voltage divider network at VO. Used for loop response measurements when output voltage is set using I2C control.
TP10Test point in voltage divider network. Used for loop response measurements when output voltage is set using external resistor divider network.
TP11Output voltage test point at VOUT connector.
TP12GND test point at VOUT connector.
(1) Absolute maximum voltage for PWRGD is 6 V. Do not use JP7 to connect to VIN for input voltages above 6 V.