SLVU135A June   2005  – June 2021 TPS62110

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification
    3. 1.3 Modifications
      1. 1.3.1 Adjustable Output IC U1 Operation
      2. 1.3.2 Fixed Output Operation
  3. 2Setup
    1. 2.1 Input / Output Connector Descriptions
    2. 2.2 Setup
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Related Documentation From Texas Instruments
  7. 6Revision History

3.1 Layout

Figure 3-1 shows the board layout for the TPS62110EVM-101 PWB.

GUID-6EB7556B-CE2D-4BC1-BA6E-7D3B03AB494A-low.gifFigure 3-1 Assembly Layer
GUID-196AB6DA-4554-4C25-96B7-0D78D26D07CC-low.gifFigure 3-2 Top Layer Routing
GUID-8C9D46E4-6C86-4C8C-B226-2CC97FDE006F-low.gifFigure 3-3 Bottom Layer Routing