SLVSC16B August   2013  – July 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Boost Controller
      2. 7.3.2 Gate-Driver Supply (VREG, EXTSUP)
      3. 7.3.3 External P-Channel Drive (GC2) and Reverse Battery Protection
      4. 7.3.4 Undervoltage Lockout and Overvoltage Protection
      5. 7.3.5 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.4.1.1 Frequency Selection and External Synchronization
        2. 7.4.1.2 Enable Inputs
        3. 7.4.1.3 Feedback Inputs
        4. 7.4.1.4 Soft-Start Inputs
        5. 7.4.1.5 Current-Mode Operation
        6. 7.4.1.6 Current Sensing and Current Limit With Foldback
        7. 7.4.1.7 Slope Compensation
        8. 7.4.1.8 Power-Good Outputs and Filter Delays
        9. 7.4.1.9 Light-Load PFM Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Boost Component Selection
        2. 8.2.2.2  Boost Maximum Input Current IIN_MAX
        3. 8.2.2.3  Boost Inductor Selection, L
        4. 8.2.2.4  Inductor Ripple Current, IRIPPLE
        5. 8.2.2.5  Peak Current in Low-Side FET, IPEAK
        6. 8.2.2.6  Right Half-Plane Zero RHP Frequency, fRHP
        7. 8.2.2.7  Output Capacitor, COUTx
        8. 8.2.2.8  Bandwidth of Boost Converter, fC
        9. 8.2.2.9  Output Ripple Voltage Due to Load Transients, ∆VOUTx
        10. 8.2.2.10 Selection of Components for Type II Compensation
        11. 8.2.2.11 Input Capacitor, CIN
        12. 8.2.2.12 Output Schottky Diode D1 Selection
        13. 8.2.2.13 Low-Side MOSFET (BOT_SW3)
        14. 8.2.2.14 BuckA Component Selection
          1. 8.2.2.14.1 BuckA Component Selection
          2. 8.2.2.14.2 Current-Sense Resistor RSENSE
        15. 8.2.2.15 Inductor Selection L
        16. 8.2.2.16 Inductor Ripple Current IRIPPLE
        17. 8.2.2.17 Output Capacitor COUTA
        18. 8.2.2.18 Bandwidth of Buck Converter fC
        19. 8.2.2.19 Selection of Components for Type II Compensation
        20. 8.2.2.20 Resistor Divider Selection for Setting VOUTA Voltage
        21. 8.2.2.21 BuckB Component Selection
        22. 8.2.2.22 Resistor Divider Selection for Setting VOUT Voltage
        23. 8.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Example 1
      2. 8.3.2 Example 2
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Converter
      2. 10.1.2 Buck Converter
      3. 10.1.3 Other Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS43330A-Q1 is ideally suited as a pre-regulator stage with low Iq requirements and for applications that must survive supply drops due to cranking events. The integrated boost controller allows the devices to operate down to 2 V at the input without seeing a drop on the buck regulator output stages. Below component values and calculations are a good starting point and theoretical representation of the values for use in the application; improving the performance of the device may require further optimization of the derived components.

8.2 Typical Application

TPS43330A-Q1 simplified_block_dgm_SLVSC16_v2.gif Figure 24. Typical Application Diagram

8.2.1 Design Requirements

The following example illustrates the design process and component selection for the TPS43330A-Q1. Table 4 lists the design-goal parameters.

Table 4. Application Example

PARAMETER VBuckA VBuckB BOOST
Input voltage VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse input) to 30 V
Output voltage, VOUTx 5 V 3.3 V 10 V
Maximum output current, IOUTx 3 A 2 A 2.5 A
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V
Current output load-step, ∆IOUTx 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Boost Component Selection

A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in its transfer function. The RHP zero relates inversely to the load current and inductor value and directly to the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the bandwidth is too close to the RHP zero frequency, the regulator becomes unstable.

Thus, for high-power systems with low input voltages, choose a low inductor value. A low value increases the amplitude of the ripple currents in the N-channel MOSFET, the inductor, and the capacitors for the boost regulator. Select these components with the ripple-to-RHP zero trade-off in mind and considering the power dissipation effects in the components due to parasitic series resistance.

A boost converter that operates always in the discontinuous mode does not contain the RHP zero in the transfer function. However, designing for the discontinuous mode demands an even lower inductor value that has high ripple currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, it becomes unstable.

TPS43330A-Q1 compensation_cx_components_boost_SLVSC16.gif Figure 25. Boost Compensation Components

8.2.2.2 Boost Maximum Input Current IIN_MAX

The maximum input current flows at the minimum input voltage and maximum load. The efficiency for VBAT = 5 V at 2.5 A is 80%, based on Figure 7.

Equation 5. TPS43330A-Q1 eq80_SLVSC16.gif

Hence,

Equation 6. TPS43330A-Q1 eq81_SLVSC16.gif

8.2.2.3 Boost Inductor Selection, L

Allow input ripple current of 40% of IIN max at VBAT = 5 V.

Equation 7. TPS43330A-Q1 eq82_SLVSC16.gif

Choose a lower value of 4 µH in order to ensure a high RHP-zero frequency while making a compromise that expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous conduction mode, where it is easier to compensate.

The inductor-saturation current must be higher than the peak-inductor current and some percentage higher than the maximum current-limit value set by the external resistive-sensing element.

Determine the saturation rating at the minimum input voltage, maximum output current, and maximum core temperature for the application.

8.2.2.4 Inductor Ripple Current, IRIPPLE

Based on an inductor value of 4 µH, the ripple current is approximately 3.1 A.

8.2.2.5 Peak Current in Low-Side FET, IPEAK

Equation 8. TPS43330A-Q1 eq83_SLVSC16.gif

Based on this peak current value, calculate the external current-sense resistor RSENSE.

Equation 9. TPS43330A-Q1 eq84_SLVSC16.gif

Select 20 mΩ, allowing for tolerance.

The filter component values RIFLT and CIFLT for current sense are 1.5 kΩ and 1 nF, respectively, which allows for good noise immunity.

8.2.2.6 Right Half-Plane Zero RHP Frequency, fRHP

Equation 10. TPS43330A-Q1 eq85_SLVSC16.gif

8.2.2.7 Output Capacitor, COUTx

To ensure stability, choose output capacitor COUTx such that

Equation 11. TPS43330A-Q1 eq86_SLVSC16.gif

Select COUTx = 680 µF.

This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms. ESR in this range is good for loop stability, because it provides a phase boost. The output filter components, L and C, create a double pole (180-degree phase shift) at a frequency fLC and the ESR of the output capacitor RESR creates a zero for the modulator at frequency fESR. One can determine these frequencies by Equation 12.

Equation 12. TPS43330A-Q1 eq87_SLVSC16.gif

This satisfies fLC ≤ 0.1 fRHP.

Potentially use a parallel configuration of smaller values to achieve this RESR or recalculate with the correct value.

8.2.2.8 Bandwidth of Boost Converter, fC

Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between stability and transient response:

fLC < fESR< fC< fRHP Zero

fC < fRHP Zero / 3

fC < fSW / 6

fLC < fC / 3

8.2.2.9 Output Ripple Voltage Due to Load Transients, ∆VOUTx

Assume a bandwidth of fC = 10 kHz.

Equation 13. TPS43330A-Q1 eq28_SLVSC16.gif

Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters are high-voltage tolerant, a higher excursion on the boost output is tolerable in some cases. In such cases, choose smaller components for the boost output.

8.2.2.10 Selection of Components for Type II Compensation

The required loop gain for unity-gain bandwidth (UGB) is

Equation 14. TPS43330A-Q1 eq88_SLVSC16.gif

The boost-converter error amplifier (OTA) has a Gm that is proportional to the VBAT voltage, which allows a constant loop response across the input-voltage range and makes compensation easier by removing the dependency on VBAT.

Equation 15. TPS43330A-Q1 eq89_SLVSC16.gif

8.2.2.11 Input Capacitor, CIN

The input ripple required is lower than 50 mV.

Equation 16. TPS43330A-Q1 eq90_SLVSC16.gif

Therefore, TI recommends 220 µF with 10-mΩ ESR or a parallel configuration of several capacitors to achieve such ESR-levels.

8.2.2.12 Output Schottky Diode D1 Selection

Maximizing efficiency requires a Schottky diode with low forward-conducting voltage (VF) over temperature and fast switching characteristics. The reverse breakdown voltage must be higher than the maximum input voltage, and the component must have low reverse leakage current. Additionally, the peak forward current must be higher than the peak inductor current. Equation 17 gives the power dissipation in the Schottky diode:

Equation 17. TPS43330A-Q1 eq91_SLVSC16.gif

8.2.2.13 Low-Side MOSFET (BOT_SW3)

Equation 18. TPS43330A-Q1 eq02_SLVSC16.gif

The times tr and tf denote the rising and falling times of the switching node and relate to the gate-driver strength of the TPS43330A-Q1 and gate Miller capacitance of the MOSFET. The first term, tr, denotes the conduction losses, which the low ON-resistance of the MOSFET minimizes. The second term, tf, denotes the transition losses which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. Transition losses are higher at high output currents and low input voltages (due to the large input peak current), and when the switching time is low.

NOTE

The ON-resistance, rDS(on), has a positive temperature coefficient, which produces the (TC = d × ΔT) term that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from MOSFET data sheets and has an assumed starting value of 0.005 per °C.)

8.2.2.14 BuckA Component Selection

8.2.2.14.1 BuckA Component Selection

Equation 19. TPS43330A-Q1 eq92_SLVSC16.gif

tON min is higher than the minimum duty cycle specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency.

8.2.2.14.2 Current-Sense Resistor RSENSE

Based on the typical characteristics for the VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose a VSENSE maximum of 50 mV.

Equation 20. TPS43330A-Q1 eq14_SLVSC16.gif

Select 15 mΩ.

8.2.2.15 Inductor Selection L

As explained in the description of the buck controllers, for optimal slope compensation and loop response, choose the inductor such that:

Equation 21. TPS43330A-Q1 eq03_SLVSC16.gif

where

  • KFLR = coil-selection constant = 200

Choose a standard value of 8.2 µH. For the buck converter, choose the inductor saturation currents and core to sustain the maximum currents.

8.2.2.16 Inductor Ripple Current IRIPPLE

At the nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IOUT max ≈ 1 A.

8.2.2.17 Output Capacitor COUTA

Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ, giving ∆VOUT(Ripple) ≈ 15 mV and a ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits.

Equation 22. TPS43330A-Q1 eq93_SLVSC16.gif
Equation 23. TPS43330A-Q1 eq94_SLVSC16.gif
Equation 24. TPS43330A-Q1 eq95_SLVSC16.gif

8.2.2.18 Bandwidth of Buck Converter fC

Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between stability and transient response.

  • Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
  • Select the zero fz ≈ fC / 10
  • Make the second pole fP2 ≈ fSW / 2

8.2.2.19 Selection of Components for Type II Compensation

TPS43330A-Q1 appinfo_selcomptyp2a_SLVSC16.gif Figure 26. Buck Compensation Components
Equation 25. TPS43330A-Q1 eq04_SLVSC16.gif

where

  • VOUT = 5 V
  • COUT = 100 µF
  • GmBUCK = 1 mS
  • VREF = 0.8 V
  • KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)

Use the standard value of R3 = 24 kΩ.

Equation 26. TPS43330A-Q1 eq05_SLVSC16.gif

Use the standard value of 1.5 nF.

Equation 27. TPS43330A-Q1 eq06_SLVSC16.gif

The resulting bandwidth of buck converter fC

Equation 28. TPS43330A-Q1 eq08_SLVSC16.gif

fC is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1

Equation 29. TPS43330A-Q1 eq07_SLVSC16.gif

fZ1 is close to the fC / 10 guideline of 5 kHz.

The second pole frequency fP2

Equation 30. TPS43330A-Q1 eq09_SLVSC16.gif

fP2 is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.

8.2.2.20 Resistor Divider Selection for Setting VOUTA Voltage

Equation 31. TPS43330A-Q1 eq10_SLVSC16.gif

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 32. TPS43330A-Q1 eq11_SLVSC16_v2.gif

and

Equation 33. TPS43330A-Q1 eq12_SLVSC16.gif

Therefore, R2 = 16 kΩ and R1 = 84 kΩ.

8.2.2.21 BuckB Component Selection

Using the same method as for VBuckA produces the following parameters and components.

Equation 34. TPS43330A-Q1 eq13_SLVSC16.gif

This result is higher than the minimum duty cycle specified (100 ns typical).

Equation 35. TPS43330A-Q1 eq15_SLVSC16.gif

∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)

Select an output capacitance COUTB of 100 µF with low ESR in the range of 10 mΩ.

Assume fC = 50 kHz.

Equation 36. TPS43330A-Q1 eq96_SLVSC16.gif
Equation 37. TPS43330A-Q1 eq97_SLVSC16.gif
Equation 38. TPS43330A-Q1 eq98_SLVSC16.gif
Equation 39. TPS43330A-Q1 eq16_SLVSC16.gif

Use the standard value of R3 = 30 kΩ.

Equation 40. TPS43330A-Q1 eq17_SLVSC16.gif
Equation 41. TPS43330A-Q1 eq18_SLVSC16.gif
Equation 42. TPS43330A-Q1 eq19_SLVSC16.gif

fC is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1

Equation 43. TPS43330A-Q1 eq21_SLVSC16.gif

fZ1 is close to the fC guideline of 5 kHz.

The second pole frequency fP2

Equation 44. TPS43330A-Q1 eq22_SLVSC16.gif

fP2 is close to the fSW / 2 guideline of 200 kHz.

Hence, the design satisfies all requirements for a good loop.

8.2.2.22 Resistor Divider Selection for Setting VOUT Voltage

Equation 45. TPS43330A-Q1 eq23_SLVSC16.gif

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 46. TPS43330A-Q1 eq24_SLVSC16.gif

and

Equation 47. TPS43330A-Q1 eq25_SLVSC16.gif

Therefore, R2 = 16 kΩ and R1 = 50 kΩ.

8.2.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs

An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole, allowing full-voltage drive of VREG to the gate with peak output current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the reference for the low-side MOSFET is the power-ground (PGNDx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum DC current IDC(max), and thermal resistance for the package.

The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gate-driver strength of the TPS43330A-Q1 and to the gate Miller capacitance of the MOSFET. The first term, tr, denotes the conduction losses, which are minimimal when the ON-resistance of the MOSFET is low. The second term, tf, denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. Transition losses are lower at low currents and when the switching time is low.

Equation 48. TPS43330A-Q1 eq26_SLVSC16.gif
Equation 49. TPS43330A-Q1 eq27_SLVSC16.gif

In addition, during the dead time (td) when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. The second term in Equation 49 denotes this dead time. Using external Schottky diodes in parallel with the low-side MOSFETs of the buck converters helps to reduce this loss.

NOTE

rDS(on) has a positive temperature coefficient, and the TC term for rDS(on) accounts for that fact. TC = d × ΔT[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and has an assumed starting value of 0.005 per ºC.

8.2.3 Application Curves

TPS43330A-Q1 Boost_Cranking_Pulse_Response.gif Figure 27. Boost Cranking Pulse Response
With 2-A Load on Boost
TPS43330A-Q1 BuckB_3_3V_400mA_1_8A_400mA.gif Figure 29. Buck Load-Step Response:
BuckB 3.3 V, 400 mA to 1.8 A to 400 mA
TPS43330A-Q1 BuckA_5V_200mA_2_4A_200mA.gif Figure 28. Buck Load-Step Response:
BuckA 5 V, 200 mA to 2.4 A to 200 mA

8.3 System Examples

The following section summarizes the previously calculated example and gives schematic and component proposals.

8.3.1 Example 1

The following example shows an application with Buck A supplying 5 V at 3 A and BuckB set to 3.3 V at 2 A. Boost-output is set to 10 V.

TPS43330A-Q1 appinfo_schematic_SLVSC16.gif Figure 30. Simplified Application Schematic, Example 1

Table 5. Application Example 1

PARAMETER VBuckA VBuckB BOOST
Input voltage VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse input) to 30 V
Output voltage, VOUTx 5 V 3.3 V 10 V
Maximum output current, IOUTx 3 A 2 A 2.5 A
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V
Current output load-step, ∆IOUTx 0.1 to 3 A 0.1 to 2 A 0.1 to 2.5 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Table 6. Application Example 1 – Component Proposals

NAME COMPONENT PROPOSAL VALUE
L1 MSS1278T-392NL (Coilcraft) 3.9 µH
L2 MSS1278T-822ML (Coilcraft) 8.2 µH
L3 MSS1278T-153ML (Coilcraft) 15 µH
D1 SK103 (Micro Commercial Components)
TOP_SW3 IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3 IRFR3504ZTRPBF (International Rectifier)
COUT1 EEVFK1J681M (Panasonic) 680 µF
COUTA, COUTB ECASD91A107M010K00 (Murata) 100 µF
CIN EEEFK1V331P (Panasonic) 220 µF

8.3.2 Example 2

The following example shows an application with lower output voltage and reduced load on BuckB (2.5 V, 1 A).

TPS43330A-Q1 appinfo_schematic3_SLVSC16.gif Figure 31. Simplified Application Schematic, Example 2

Table 7. Application Example 2

PARAMETER VBuckA VBuckB BOOST
Input voltage VIN = 5 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
VBAT = 5 V (cranking pulse input) to 30 V
Output voltage, VOUTx 5 V 2.5 V 10 V
Maximum output current, IOUTx 3 A 1 A 2 A
Load-step output tolerance, ∆VOUT + ∆VOUT(Ripple) ±0.2 V ±0.12 V ±0.5 V
Current output load-step, ∆IOUTx 0.1 to 3 A 0.1 to 1 A 0.1 to 2 A
Converter switching frequency, fSW 400 kHz 400 kHz 200 kHz

Table 8. Application Example 2 – Component Proposals

NAME COMPONENT PROPOSAL VALUE
L1 MSS1278T-392NL (Coilcraft) 3.9 µH
L2 MSS1278T-822ML (Coilcraft) 8.2 µH
L3 MSS1278T-223ML (Coilcraft) 22 µH
D1 SK103 (Micro Commercial Components)
TOP_SW3 IRF7416 (International Rectifier)
TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)
BOT_SW3 IRFR3504ZTRPBF (International Rectifier)
COUT1 EEVFK1V471Q (Panasonic) 470 µF
COUTA ECASD91A157M010K00 (Murata) 150 µF
COUTB ECASD40J107M015K00 (Murata) 100 µF
CIN EEEFK1V331P (Panasonic) 330 µF