SLVSAR7E June   2011  – October 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.3.1.1 Frequency Selection and External Synchronization
        2. 7.3.1.2 Enable Inputs
        3. 7.3.1.3 Feedback Inputs
        4. 7.3.1.4 Soft-Start Inputs
        5. 7.3.1.5 Current-Mode Operation
        6. 7.3.1.6 Current Sensing and Current Limit With Foldback
        7. 7.3.1.7 Slope Compensation
        8. 7.3.1.8 Power-Good Outputs and Filter Delays
        9. 7.3.1.9 Light-Load PFM Mode
      2. 7.3.2 Frequency-Hopping Spread Spectrum (TPS43351-Q1 Only)
      3. 7.3.3 Gate-Driver Supply (VREG, EXTSUP)
      4. 7.3.4 External P-Channel Drive (GC2) and Reverse-Battery Protection
      5. 7.3.5 Undervoltage Lockout and Overvoltage Protection
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  BuckA Component Selection
          1. 8.2.2.1.1 Minimum ON Time, tON min
          2. 8.2.2.1.2 Current-Sense Resistor RSENSE
        2. 8.2.2.2  Inductor Selection L
        3. 8.2.2.3  Inductor Ripple Current IRIPPLE
        4. 8.2.2.4  Output Capacitor COUTA
        5. 8.2.2.5  Bandwidth of Buck Converter fC
        6. 8.2.2.6  Selection of Components for Type II Compensation
        7. 8.2.2.7  Resistor Divider Selection for Setting VOUTA Voltage
        8. 8.2.2.8  BuckB Component Selection
        9. 8.2.2.9  Resistor Divider Selection for Setting VOUT Voltage
        10. 8.2.2.10 BUCKx High-Side and Low-Side N-Channel MOSFETs
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Buck Converter
      2. 10.1.2 Other Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TPS4335x-Q1 devices are dual synchronous buck controllers used to convert a higher-input voltage to two lower-output voltages. The following sections have the component values and calculations that are a good starting point for use in the application. Some of the values in the equations are theoretical values, to improve the performance of the device may require further optimization of these values.

Typical Application

TPS43350-Q1 TPS43351-Q1 typ2_app_sch_lvsar7.gif Figure 14. Simplified Application Schematic Example

Design Requirements

Table 3 lists the design-goal parameters.

Table 3. Design Parameters

PARAMETER VBuckA VBuckB
Input voltage VIN = 6 V to 30 V
12 V - typical
VIN = 6 V to 30 V
12 V - typical
Output voltage, VOUTx 5 V 3.3 V
Maximum output current, IOUTx 3 A 2 A
Load step output tolerance, ∆VOUT + ∆VOUT(Ripple) ±0.2 V ±0.12 V
Current output load step, ∆IOUTx 0.1 A to 3 A 0.1 A to 2 A
Converter switching frequency, fSW 400 kHz 400 kHz

Detailed Design Procedure

The following example illustrates the design process and component selection for the TPS43350-Q1.

This is a starting point, and theoretical representation of the values to be used for the application; improving the performance of the device may require further optimization of the derived components.

Table 4. Application Example – Component Proposals

NAME COMPONENT PROPOSAL VALUE
L1 MSS1278T-822ML (Coilcraft) 8.2 µH
L2 MSS1278T-153ML (Coilcraft) 15 µH
D1 SK103 (Micro Commercial Components)
SWRB IRF7416 (International Rectifier)
SWAH, SWAL, SWBH, SWBL Si4840DY-T1-E3 (Vishay)
COUTA, COUTB ECASD91A107M010K00 (Murata) 100 µF
CIN EEEFK1V331P (Panasonic) 330 µF

BuckA Component Selection

Minimum ON Time, tON min

Equation 5. TPS43350-Q1 TPS43351-Q1 eq92_lvsar7.gif

This is higher than the minimum on-time specified (100 ns typical). Hence, the minimum duty cycle is achievable at this frequency.

Current-Sense Resistor RSENSE

Based on the typical characteristics for VSENSE limit with VIN versus duty cycle, the sense limit is approximately 65 mV (at VIN = 12 V and duty cycle of 5 V / 12 V = 0.416). Allowing for tolerances and ripple currents, choose VSENSE with a maximum of 50 mV.

Equation 6. TPS43350-Q1 TPS43351-Q1 eq14_lvsa82.gif

Select 15 mΩ.

Inductor Selection L

As explained in the description of the buck controllers, for optimal slope compensation and loop response, the inductor should be chosen such that:

Equation 7. TPS43350-Q1 TPS43351-Q1 eq03_lvsa82.gif

KFLR = Coil selection constant = 200

Choose a standard value of 8.2 µH. For the buck converter, the inductor saturation currents and core should be chosen to sustain the maximum currents.

Inductor Ripple Current IRIPPLE

At nominal input voltage of 12 V, this inductor value causes a ripple current of 30% of IO max ≈ 1 A.

Equation 8. TPS43350-Q1 TPS43351-Q1 eq7a_lvsar7.gif

where

  • VIN = Input voltage
  • VOUT = Output voltage
  • fSW = Switching frequency
  • L = Inductor

Output Capacitor COUTA

Select an output capacitance COUTA of 100 µF with low ESR in the range of 10 mΩ. This gives ∆VO(Ripple) ≈ 15 mV and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the required limits.

Equation 9. TPS43350-Q1 TPS43351-Q1 eq93_lvsa82.gif
Equation 10. TPS43350-Q1 TPS43351-Q1 eq94_lvsa82.gif
Equation 11. TPS43350-Q1 TPS43351-Q1 eq95_lvsa82.gif

Bandwidth of Buck Converter fC

Use the following guidelines to set frequency poles, zeroes and crossover values for a tradeoff between stability and transient response.

  • Crossover frequency fC between fSW / 6 and fSW / 10. Assume fC = 50 kHz.
  • Select the zero fz ≈ fC / 10.
  • Make the second pole fP2 ≈ fSW / 2.

Selection of Components for Type II Compensation

TPS43350-Q1 TPS43351-Q1 appinfo_selcomptyp2a_lvsar7.gif Figure 15. Buck Compensation Components
Equation 12. TPS43350-Q1 TPS43351-Q1 eq04_lvsa82.gif

Use the standard value of R3 = 24 kΩ,

Where VOUT = 5 V, COUTx = 100 µF, GmBUCK = 1 mS, VREF = 0.8 V

KCFB = 0.125 / RSENSE = 8.33 S (0.125 is an internal constant)

Equation 13. TPS43350-Q1 TPS43351-Q1 eq05_lvsa82.gif

Use the standard value of 1.5 nF.

Equation 14. TPS43350-Q1 TPS43351-Q1 eq06_lvsa82.gif

The resulting bandwidth of buck converter, fC:

Equation 15. TPS43350-Q1 TPS43351-Q1 eq08_lvsa82.gif

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1:

Equation 16. TPS43350-Q1 TPS43351-Q1 eq07_lvsa82.gif

This is close to the fC / 10 guideline of 5 kHz.

The second pole frequency fP2:

Equation 17. TPS43350-Q1 TPS43351-Q1 eq09_lvsa82.gif

This is close to the fSW / 2 guideline of 200 kHz. Hence, the design satisfies all requirements for a good loop.

Resistor Divider Selection for Setting VOUTA Voltage

Equation 18. TPS43350-Q1 TPS43351-Q1 eq10_lvsa82.gif

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 19. TPS43350-Q1 TPS43351-Q1 eq11_lvsa82.gif

and

Equation 20. TPS43350-Q1 TPS43351-Q1 eq12_lvsa82.gif

Therefore, R2 = 16 kΩ and R1 = 84 kΩ.

BuckB Component Selection

Using the same method as for VBuckA produces the following parameters and components.

Equation 21. TPS43350-Q1 TPS43351-Q1 eq13_lvsar7.gif

This is higher than the minimum duty cycle specified (100 ns typical).

Equation 22. TPS43350-Q1 TPS43351-Q1 eq15_lvsa82.gif

∆Iripple current ≈ 0.4 A (approximately 20% of IOUT max)

Select an output capacitance CO of 100 µF with low ESR in the range of 10 mΩ. Assume fC = 50 kHz.

Equation 23. TPS43350-Q1 TPS43351-Q1 eq96_lvsa82.gif
Equation 24. TPS43350-Q1 TPS43351-Q1 eq97_lvsa82.gif
Equation 25. TPS43350-Q1 TPS43351-Q1 eq98_lvsa82.gif
Equation 26. TPS43350-Q1 TPS43351-Q1 eq16_lvsa82.gif

Use the standard value of R3 = 30 kΩ.

Equation 27. TPS43350-Q1 TPS43351-Q1 eq17_lvsa82.gif
Equation 28. TPS43350-Q1 TPS43351-Q1 eq18_lvsa82.gif
Equation 29. TPS43350-Q1 TPS43351-Q1 eq19_lvsa82.gif

This is close to the target bandwidth of 50 kHz.

The resulting zero frequency fZ1:

Equation 30. TPS43350-Q1 TPS43351-Q1 eq21_lvsa82.gif

This is close to the fC guideline of 5 kHz.

The second pole frequency fP2:

Equation 31. TPS43350-Q1 TPS43351-Q1 eq22_lvsa82.gif

This is close to the fSW / 2 guideline of 200 kHz.

Hence, the design satisfies all requirements for a good loop.

Resistor Divider Selection for Setting VOUT Voltage

Equation 32. TPS43350-Q1 TPS43351-Q1 eq23_lvsa82.gif

Choose the divider current through R1 and R2 to be 50 µA. Then

Equation 33. TPS43350-Q1 TPS43351-Q1 eq24_lvsa82.gif

and

Equation 34. TPS43350-Q1 TPS43351-Q1 eq25_lvsa82.gif

Therefore, R2 = 16 kΩ and R1 = 50 kΩ.

BUCKx High-Side and Low-Side N-Channel MOSFETs

An internal supply, which is 5.8 V typical under normal operating conditions, provides the gate-drive supply for these MOSFETs. The output is a totem pole allowing full voltage drive of VREG to the gate with peak output current of 1.5 A. The reference for the high-side MOSFET is a floating node at the phase terminal (PHx), and the reference for the low-side MOSFET is the power-ground (PGx) terminal. For a particular application, select these MOSFETs with consideration for the following parameters: rDS(on), gate charge Qg, drain-to-source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.

The times tr and tf denote the rising and falling times of the switching node and have a relationship to the gate-driver strength of the TPS43350x-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction losses, which are minimal when the on-resistance of the MOSFET is low. The second term denotes the transition losses, which arise due to the full application of the input voltage across the drain-source of the MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.

Equation 35. TPS43350-Q1 TPS43351-Q1 eq26_lvsa82.gif
Equation 36. TPS43350-Q1 TPS43351-Q1 eq27_lvsa82.gif

In addition, during dead time td when both the MOSFETs are off, the body diode of the low-side MOSFET conducts, increasing the losses. The second term in the foregoing equation denotes this. Using external Schottky diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.

NOTE

The rDS(on) has a positive temperature coefficient, and TC term for rDS(on) accounts for that fact. TC = d × delta T[°C]. The temperature coefficient d is available as a normalized value from MOSFET data sheets and can be assumed to be 0.005 / °C as a starting value.

Application Curves

TPS43350-Q1 TPS43351-Q1 g_buck_load_step_forced_cont_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 16. Buck Load Step: Forced Continuous Mode (Moved Here)
(0 To 4 A at 2.5 A/µs)
TPS43350-Q1 TPS43351-Q1 g_buck_load_step_low_power_exit_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
LÄ = 4.7 µH RSENSE = 10 mΩ
Figure 18. Buck Load Step: Low-Power-Mode Exit
90 mA to 4 A at 2.5 A/µs (Moved Here)
TPS43350-Q1 TPS43351-Q1 g_buck_load_step_low_power_entry_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 17. Buck Load Step: Low-Power-Mode Entry
4 A to 90 mA at 2.5 A/µs (Moved Here)