SLVAFF0 September   2022 TPS25947 , TPS2597 , TPS25981 , TPS25982 , TPS25985

 

  1.   Abstract
  2.   Trademarks
  3. 1Understanding the FET SOA
  4. 2Ensuring FET SOA in Hot-Swap Design
  5. 3eFuse Ensuring Integrated FET SOA Operation
    1. 3.1 Thermal Shutdown
    2. 3.2 eFuse Response to Events Stressing Integrated FET
  6. 4Plotting eFuse AOA
  7. 5eFuse Application Design Recommendations to Ensure Integrated FET Reliability
  8. 6Summary
  9. 7References

1 Understanding the FET SOA

SOA defines the maximum value of VDS, IDS, and time envelope of operation which the device can be expected to operate without getting damaged.

Figure 1-1 Data Sheet SOA of the CSD19536KTT

The entire SOA is made up of five distinct limitations, each of which shape the overall curve, as shown in Figure 1-1, the SOA for TI’s 100 V D2PAK CSD19536KTT.

Four of these limitations can be easily calculated from the known FET parameters – the RDS(ON) limit, the current limit, the maximum power limit, and the BVDSS limit.

  • RDS(ON) limit is the maximum RDS(ON) of FET at maximum operating junction temperature.
  • Current limit is constrained because of maximum rated junction temperature, package capability and other factors. This region can also be called electrical SOA.
  • For power limit calculation, the temperature rise for a given pulse duration is calculated using transient thermal impedance plot in the FET data sheet. Power profile which gives temperature rise close to the maximum junction temperature decides the boundary of the SOA curve. Power limit region can also be referred as thermal SOA.
  • BVDSS limit is the FET breakdown voltage, defined by FET technology and comes under electrical SOA.

The fifth and the most critical region is the thermal instability region, which cannot be determined with formulas, but must be tested. This portion of the SOA, noted by where the curve deviates from the constant power line that necessarily has a slope of -1 on a current vs. voltage log-log scale, indicates where thermal runaway can occur. The steeper the slope, the more prone the FET is to enter into thermal runaway condition at higher operating voltages. This region can also be called electro-thermal SOA as explained in Section 3. To plot thermal instability region there are two methods:

  1. The most accurate method is the measurement method which is followed at TI. Computer-aided test system is used for the measurement. The FET is stressed with a known current and VDS pulse of certain time duration. If the FET survives this pulse then the drain to source current is increased. This process is repeated till the FET fails.
  2. Another method is power limit calculation where the boundary is calculated based on safe junction temperature rise. This method is not an accurate method and does not present true picture of thermal instability region.

After having looked in detail about FET SOA , here are some FET failure modes that can occur on violating SOA.

  1. BVDSS violation - Causes reverse-biased body-drift diode break down and large amount of current starts to flow between the source and drain due to the avalanche multiplication process.
  2. Power limit violation - On operating FET for higher power than the SOA boundary for a given time causes die junction temperature to cross the safe threshold and FET will damage due to excessive heat.
  3. Current limit violation - Current limit is a function of maximum junction temperature, internal materials and connection between silicon and plastic package. Violating this can cause failure mechanisms such as excessive heating up of die, wire infusion, thermal degradation of molding compound, and electromigration.

Overall, it can be shown that the violation of maximum junction temperature specification of FET causes the FET to fail. Ensuring FET junction temperature is always at a safe level, also helps in ensuring that FET operates in SOA.