The TPS62903 is a very flexible synchronous step-down DC/DC converter. If its flexibility is used in the right way, power designers can get the smallest application size possible. This section discusses how to best configure TPS62903 for smaller possible area . When talking about the solution size of a buck converter, there are three elements to consider:

1. The DC/DC buck converter package and pinout: The TPS62903 device is available in a small nine-pin VQFN package measuring 1.50 mm × 2.00 mm. The device footprint covers only 3 mm² which helps on reducing the total solution size. The TPS62903 has an optimized pinout for easy layout and placement of external components. Having the sensing pins on the bottom side of the package allows placing the sensing components away from power traces and the switch node. Having VIN on the left side and SW and VOUT on the right side of the package makes it easy to place the input capacitor, the inductor, and output capacitor near the package efficiently.
2. The inductor: The inductor is one of the biggest external components on the buck power supply design. Choosing the right inductor for the application is a big contributor to reduce the solution size. A selectable switching frequency of 2.5 MHz or 1.0 MHz allows the use of small inductors. The device is designed for a nominal 1 µH inductor. Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact on efficiency, transient response, cost, and inductor size. Smaller values than 1 µH will cause a larger inductor current ripple which causes larger negative inductor current in forced PWM mode at low or no output current. Therefore, they are not recommended at large voltages across the inductor as it is the case for high input voltages and low output voltages. Low output current in forced PWM mode causes a larger negative inductor current peak which can exceed the negative current limit. There are many 1 µH small inductors that come as small as 2.0 mm × 1.6 mm size.
3. Other components:
   • Input capacitor: Only one 10 µF input capacitor is needed. Since the TPS62903 supports input voltages between 3–17 V, a 25 V rating is enough to support the full input voltage range. If the input voltage can be limited, then a lower voltage rating capacitor can be used. Typically, the designer should choose a voltage rating of about 50% above the maximum voltage the capacitor will see at any given time. An 0805-size, low-ESR multilayer ceramic capacitor (MLCC) is recommended for best filtering and should be placed between VIN and GND as close as possible to those pins.
   • Output capacitor: Only one 22 µF output capacitor is recommended. The DCS-Control architecture of the device allows for a tiny ceramic output capacitor to be used. The DC rating of the capacitor can be as low as 10 V since the V_OUT is limited to 5.5 V.
   • Soft start capacitor: The device provides the user the option to program the start-up time of output voltage. However, to save space, the user can use the pre-programmed soft start time and leave the pin open.
   • Feedback loop: This is one of the advantages of the TPS62903. There is no need for external feedback loop as long as the needed output voltage is one of the 16 provided options in the VSET Selection Table of the TPS62903, 3-V to 17-V, High Efficiency and Low IQ Buck Converter in 1.5-mm × 2-mm Data Sheet. By selecting the VSET option using the MODE/S-CONF pin, and picking one of the 16 options using the resistor from VSET to GND, it allows the user to save space and improve solution accuracy. The VSET option has better accuracy as it does not include the accuracy of the external feedback resistors. For typical E96 resistors, the accuracy is about ±1%, plus an additional ±0.9% of the reference, so the total accuracy of the external feedback option is ±1.9%. On the other side, if VSET is used, then only ±1.25% of the internal loop accuracy needs to be taken into consideration.
   • Precision enable (EN): The TPS62903 does not require any pullup resistor. The user can connect the EN pin directly to VIN, this reduces the need for another external component. The precise enable input allows the user to program the undervoltage lockout by adding a resistor divider to the input of the enable pin.
   • Power Good (PG): This is an optional feature too. If the PG pin is not used, then it can be open to save space. This feature is used to indicate whether the output voltage has reached its target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level.

This section describes how to best design a buck converter to support 6 V input supply, and step it down to 1.2 V output and support up to 3 A. The same steps can be taken to design it for other design requirements.

Selection of components:

• Inductor: The 6 V_IN to 1.2 V output voltage allows the use of 0.68 µH inductor with reasonable inductor current ripple if 2.5 MHz is chosen. A small size 2.0 mm × 1.6 mm 0.68 µH inductor can be used for this such as the “DFE201612E-R68M#” from Murata.
• Input capacitor: Input voltage requirement for this design is only 6 V. Therefore, 10 µF with only 10 V rating can be used.
• Output capacitor: The recommended output capacitor in the data sheet is 22 µF. In this example, the output is set to 1.2 V, therefore only 6 V voltage rating can be used.
• Feedback: 1.2 V V_OUT is one of the 16 options VSET can support, to save area and achieve better accuracy, the internal voltage divider can be used in this example. Internal feedback should give a total system accuracy of ±1.25% versus 1.9% if external feedback is used.
• Mode and Smart Configuration: A low V_OUT can tolerate low switching frequency with good inductor current ripple. Both 1 MHz or 2.5 MHz can be chosen. However, the goal is to have the smallest solution size possible, and 2.5 MHz allows the use of a 0.68 µH inductor with acceptable ripple. Power save mode is preferred to provide high efficiency at light loads. Thus, 26.1 kΩ is connected on the Mode/S-CONF pin to GND.
• EN, Soft start, and PG: If there is no need for soft start capacitor and Power Good features, these pins can be left floating. The EN pin can be connected directly to VIN. These add some additional BOM savings.

Here is a suggested schematic for this example:

Figure 1-2 provides a layout example. CIN, COUT, and the inductor L are placed as close as possible to the pin of the device. The SW node trace is kept small for better noise performance. Vias are added on GND, VIN, and VOUT traces to help improve thermal dissipation of the board.

Switching regulators are best known for their good efficiency. However, there are many power loss factors that contribute into the total losses; therefore, they impact the efficiency. To select the highest efficiency design, it is helpful to understand the basic mechanisms of power loss. This section explores some major power loss factors and discusses how to reduce their losses by making some design tradeoffs and choices.