D-CAP series control schemes are widely used in notebook, server, EP power and many other areas due to the advantages of good dynamic performance and less external components [1-2]. The zero formed by output capacitor ESR is used for loop compensation in the original D-CAP control [3- 4]. For some application with small ESR output capacitor, the zero generated by the internal ripple injection circuit can be used for compensation instead of the ESR zero in D-CAP2/D-CAP3 control. In the previous application report https://www.ti.com/lit/pdf/SLVAF11, it is introduced that a simplified method for D-CAP2/D-CAP3 converter stability design is to ensure the ripple injection zero inside bandwidth [5]. On the basis, the output capacitor selection limits are deducted for application design. However, the bandwidth will decrease with increasing output voltage in D-CAP control loop and the ripple injection zero is hard to be kept inside bandwidth. In this condition, the feedforward capacitor, that can provide an additional pair of zero and pole in the loop, can be used to ensure system stability. The detailed analysis and selection method of feedforward capacitor C_ff are introduced in this application report.

The bode plots of D-CAP2/D-CAP3 converters are shown as Figure 2-1. After the LC double poles frequency ω₀ related with inductance and output capacitance, the slope of loop gain can be approximately seen as changing from 0 to -40dB/decade. With the zero injected by the internal ripple injection circuit, the slope becomes – 20dB/decade at 0dB, which could bring sufficient phase margin [7].

Figure 2-1 Bode Plot of (a) D-CAP2 (b) D-CAP3 Converter

For a stable D-CAP2/3 converter, if output voltage is increased with no other changes, the system will tend to become unstable, as shown in Figure 2-2. Since the gain before double poles frequency equals to A_cp*V_ref/V_o, system gain and crossover frequency ω_cross will decrease with increasing V_o. If ω_cross becomes lower than the frequency of ripple injection zero ω_RI, system will have a -40dB/decade slope at 0dB, which may cause insufficient phase margin.

Figure 2-2 Loop Gain of a D-CAP2 Converter (a) low V_o with -20dB/Decade Crossing (b) high V_o with -40dB/Decade Crossing

For some D-CAP2/3 converters similar to TPS548D22, the ripple injection zero frequency ω_RI is adjustable with external configuration (sometimes named as ramp time constant, the ramp here is the ripple injection, time constant is the reciprocal of angular frequency). For TPS548D22, the V_ref can also be adjusted for different output voltage to change ω_cross. Those features can both help to adjust the relation of ω_cross and ω_RI and achieve -20dB/decade crossing.

But for most D-CAP2/3 devices to achieve easy design, the ripple injection zero frequency and reference voltage are fixed. So the LC double poles frequency ω₀ must be increased for bandwidth improvement to ensure -20dB/decade slope at 0dB, as shown in Figure 2-3. However, it can be seen from Equation 1 that the inductance and output capacitance must be reduced to increase LC double poles frequency, which will cause large output ripple and noise. That causes the contradiction between output ripple and stability for D-CAP2/3 converters.

Equation 1.

Figure 2-3 Loop Gain of a D-CAP2 Converter (a) High V_o with -40dB/Decade Crossing (b) Reducing L or C_o for -20dB/Decade Crossing

In application report https://www.ti.com/lit/pdf/SLVAF11, TPS568230 was used as an example to illustrate the stability design method for a 1.5 V V_o low output voltage application. Here the case with 5 V V_o is shown to reflect the contradiction between output ripple and stability in high output voltage application.

The condition for analysis is: V_in=12 V, V_o=5 V, I_outmax=8 A, f_sw=600kHz. First, the range of inductance can be got as 1.52uH-3.04uH, according to the principle to limit inductor current ripple as 20%-40% of I_outmax.

Select inductor 744311220 L=2.2uH. Based on the previous proposed selection method of output capacitor, we could get the limits of C_o as 4.7uF-22.3uF. With the upper limit C_o=22.3uF, the output voltage ripple is too large to meet the requirement for lots of application.

It is obvious that reducing L or C_o is just a trade-off solution between output voltage ripple and stability. Compared to that, adding feedforward capacitor C_ff is a better solution to ensure converter stability.

Figure 3-1 Scheme of Feedback Divider Including Feedforward Capacitor

The effects of adding feedforward capacitor in the feedback divider are studied in the application report [6]. A feedback divider including C_ff is shown as Figure 3-1. C_ff will introduce a pair of zero and pole in the converter loop. The angular frequency of the introduced zero and pole are:

Equation 2.

Equation 3.

The effects of the zero and pole introduced by C_ff are shown as Figure 3-2.

C_ff has both effects on the loop gain and phase. The loop gain is increased to boost bandwidth and optimize transient response. Also, the phase is boosted to increase the phase margin for system stability.

In application notes [2,8], some methods have been proposed to use C_ff for phase margin enhancement. But in those methods, the bode plot results without C_ff are always needed to get recommended C_ff value. That feature makes those C_ff selecting methods more applicable in the solution validation process but not in the application design process.

A new method to choose C_ff is proposed in this application report. The bode plot results without C_ff are not needed to get the recommended C_ff value in this method, which makes it more applicable in application design.

This method is implemented by letting the gain cross 0dB with -20dB/decade slope [7]. To be noted, -20dB/decade gain at 0dB is not a necessary condition for stability. So this method just provides an allowable range for C_ff and it doesn’t mean the converter will be unstable if C_ff exceeds this range.

For the case as Figure 4-1(a) when the ripple injection zero frequency ω_RI is larger than bandwidth, we can add the C_ff zero ω_z inside bandwidth, then the loop gain can cross 0dB with -20dB/decade, as shown in Figure 4-1(b).

In the case as Figure 4-2, the zero and pole introduced by C_ff are both added inside bandwidth and the system stability can still be ensured. Although the slope of loop gain becomes -40dB/decade again after the pole ω_p, the loop gain increasement with C_ff makes the bandwidth increased and the ω_RI becomes smaller than bandwidth. A -20dB/decade crossing is achieved and system will have enough phase margin.

In the case as Figure 4-3, both the zero and pole introduced by C_ff are inside bandwidth, but the ripple injection zero frequency ω_RI is still larger than the bandwidth. At this condition, the loop gain will still cross 0dB with -40dB/decade, which can’t ensure the system phase margin.

Above all, we can conclude two restrictions to achieve a stable state with -20dB/decade crossing after adding feedforward capacitor:

A. ω_z<ω_cross; B. avoiding the condition as Figure 4-3.

First we could deduct the limit for restriction A. Based on Figure 4-4, we can know that ω_z<ω_cross can be achieved by ensuring ω_z<ω_c. The expression of ω_c is as equation (4). With equations (2) and (4), the lower limit of C_ff is derived as equation (5).

Figure 4-4 D-CAP2 Converter Loop Gain When Adding ω_z< ω_cross

Equation 4.

Equation 5.

To get the limits for restriction B, we could know that Equation 6 corresponds the condition as Figure 4-3. Then the restriction B to avoid that condition corresponds to Equation 7.

Equation 6.

Equation 7.

where A_p is the amplitude of gain at ω_p.

To get the expressions of A_p and ω_cross, we can first get the relation between gain and frequency as Equation 8 through Equation 10.

Equation 8.

Equation 9.

Equation 10.

Substituting Equation 2 through Equation 3 into Equation 8 through Equation 10, the expressions of A_p and ω_cross can be received as Equation 11 and Equation 12.

Equation 11.

Equation 12.

Substituting Equation 11 and Equation 12 into Equation 7, we can get Equation 13 as equation for restriction B.

Equation 13.

Combine the Equation 5 for restriction A and Equation 13 for restriction B, Equation 14 and Equation 15 are the limits for C_ff.

Equation 14.

Equation 15.

At the meantime, the bandwidth after adding C_ff should also be limited under 1/3*f_sw. Since it is hard to give a unified method for the estimation of bandwidth and phase margin after adding C_ff, it is suggested to verify with the help of simulation model or bench loop test results.

Figure 5-1 is the design flow chart for D-CAP2/D-CAP3 converter with C_ff. All the inductance and capacitance used in choosing C_ff are effective value considering degrading.

Here TPS568230 is used as an example to illustrate the design method for a 5V V_o application. The condition of example is V_in=12 V, V_o=5 V, I_outmax=8 A, f_sw=600kHz.

First select voltage divider resistors R₁(R_top)=220 kΩ and R₂(R_bottom)=30 kΩ to achieve 5 V output with 0.6 V reference voltage. Then, same as the analysis mentioned in section 2, the range of inductance can be got as 1.52 uH-3.04 uH, according to the principle to limit inductor current ripple as 20%-40% of I_outmax. And we can select 744311220 inductor and its effective inductance with 8 A current is about 1.8 uH.

About 180uF output capacitance are used to meet output ripple requirement. Here the 885012108012 MLCC are used. With about 52.5% degrading at 5 V bias for the 47 uF capacitance, the effective capacitance of each MLCC is about 22.35 uF. Capacitance of 8 parallel MLCCs are 178.8 uF.

Then the method is used to select C_ff. As A_cp=29.3 and ω_RI=270 k for TPS568230, we can get C_ff>44 pF according to Equation 14 and Equation 15. Here we can choose 120 pF C_ff.

The bode plot test result with 180 uF output capacitors and no C_ff is shown in Figure 6-1 for comparison. It could be seen that the phase margin is 17.228 degree. The crossover frequency is about 18.54 kHz.

Figure 6-1 Experimental Result without Cff

Figure 6-2 shows the validation result with chosen C_ff=120 pF using the proposed method. It can be seen that bandwidth is increased from 18.54 kHz to 47.22 kHz, while the phase margin is increased from 17.228 degree to 75.353 degree. Both dynamic performance and stability can be enhanced with the 120 pF C_ff. That proves the effectiveness of the proposed method.

Figure 6-2 Experimental Verification of Proposed Method

A selection method of feedforward capacitor is proposed in this application report for D-CAP2/D-CAP3 converters based on loop stability analysis. First, the necessity of adding C_ff in some application with high output voltage is analyzed. Then the impacts of the C_ff on the converter loop is introduced and a method to choose C_ff for stability is proposed by ensuring -20dB/decade gain slope at gain crossover frequency. Compared with previous methods, the bode plot test results without C_ff aren’t needed to get recommended C_ff value, which makes the method more applicable in application design process. Finally, a detailed flow chart is given to help designing application of D-CAP2/D-CAP3 converter. The proposed method is verified by experiments.

For TPS568230 I_outmax=8 A, V_ref=0.6 V. C_o in the table are effective value considering degrading. The large C_ff as 1000 pF can be allowed from loop stability view, but it could inject more high frequency noise into feedback and also might affect converter operation. The C_ff theoretical calculation methods must be used combined with real situation and bench test results.