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  • Parallel Operation of TPS2663 eFuses

    • SLVAF13 November   2020 LM5069 , TPS1663 , TPS2663

       

  • CONTENTS
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  • Parallel Operation of TPS2663 eFuses
  1.   Trademarks
  2. 1Introduction
  3. 2Parallel Configuration
  4. 3Design Example
    1. 3.1 Design Requirements
    2. 3.2 Detailed Design Procedure
    3. 3.3 Performance Results
  5. 4Comparison With the Hot-Swap and ORing Controller Solution
  6. 5TPS16630 Parallel Circuit Configuration
  7. 6Conclusion
  8. 7References
  9. IMPORTANT NOTICE
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APPLICATION NOTE

Parallel Operation of TPS2663 eFuses

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

The TPS2663 device incorporates protection features such as inrush current management, adjustable overcurrent limit, short-circuit protection, overvoltage and input reverse polarity protection. Figure 1-1 shows an application schematic of the TPS26631 feeding a downstream DC-DC converter in a PLC system. The capacitor CdVdT on the dVdT pin sets the output voltage slew-rate and hence the inrush current level where as the resistor RILIM sets the current limit (ILIM) which the device needs to limit to under fault conditions. The device offers a B-FET driver to control an external N-channel FET ‘Q1’ for reverse current and reverse polarity protection which simplifies designs requiring class-A performance during system tests like IEC61000-4-5 surge tests as well as input supply brown-out tests.

The maximum current the TPS2663 can support is up to 6 A. However the device can be used in parallel configuration with multiple TPS2663 devices to achieve higher output currents which is often required in many industrial systems. This report presents how the TPS2663 can be used in parallel operation to achieve higher output currents as well as to demonstrate the performance benefits it brings to the system with its integrated protection functions.

Figure 1-1 Application Schematic of TPS26631 for Power Path Protection in a PLC System

2 Parallel Configuration

The basic principle of eFuse parallel operation and the design considerations are covered in the Achieve 20-A Circuit Protection and Space Efficiency Using Paralleled eFuses Application Report(1). The same concept is applicable for TPS26631 parallel operation. The key points from the Achieve 20-A Circuit Protection and Space Efficiency Using Paralleled eFuses Application Report(1) are summarized in the rest of this section in the context of TPS26631.

  • During start-up, equal current sharing among the parallel-connected eFuses is needed to ensure successful start-up. To achieve that,
    • The UVLO, OVP, SHDNb pins of all the parallel-connected eFuses are connected together for synchronizing the ON or OFF operation
    • The dVdT pins of all the eFuses are connected together to ensure uniform output ramp rate and equal dynamic power stress
  • During steady-state operation, the current sharing is decided by the RDS(on) mismatch. The device having the lower RDS(on) shares more current than the rest of the devices. However, the self-heating effect due to positive temperature characteristics of the MOSFET helps to a larger extent towards equal load current distribution in parallel configuration.
  • During overload operation, the inherent current source characteristic of eFuse forces all the parallel-connected eFuses to operate in current-limiting mode. For the TPS26631, each device should have its own current-limiting resistor (RILIM) as demanded by the internal current loop architecture.
Figure 2-1 Circuit Configuration of Two TPS26631 Devices in Parallel
GUID-20201025-CA0I-CGVK-CZ85-TTQRBPL7P0XQ-low.png Figure 2-2 Current Sharing Between the Devices During Start-up in dVdT mode

Figure 2-1 illustrates the circuit configuration of two TPS26631 devices in parallel. A single blocking FET Q1 on the primary eFuse is enough for reverse current blocking. Figure 2-2 shows the current sharing during start-up with dVdT pins together. Even though the ramp rate of the dVdT pin is the same for both the devices, the mismatch in the internal dVdT gain and the internal FET characteristics leads to unequal current sharing during start-up. For uniform current distribution while starting up into large loads, current limited start-up is recommended as follows

  • Leave dVdT pins OPEN
  • Use RILIM resistor switch network at the ILIM pin. The RILIM_Low sets the inrush current. After successful start-up, PGOOD asserts high which sets the overload current limit as per (RILIM_Low || RILIM_High) at the ILIM pin

The modified parallel circuit configuration is illustrated in Figure 2-3 and the corresponding start-up waveform demonstrating equal start-up current between two TPS26631 devices is shown in Figure 2-4. In this application report, RILIM resistor switch network is considered in the design example as it ensures uniform current sharing under all the stressful events.

Figure 2-3 Parallel Configuration of TPS26631 With RILIM Switch Network at ILIM Pins
GUID-20201025-CA0I-HH6J-NZKL-HRZ73ZX7KCQZ-low.png Figure 2-4 Current Sharing Between the Devices During Start-up in Current-Limit Mode

3 Design Example

An example of designing four TPS26631 eFuse parallel circuits is considered in this section.

3.1 Design Requirements

Table 3-1 shows the design parameters for this application example.

Table 3-1 Design Parameters
Design Parameter Example Value
Typical input voltage, VIN 24 V
Undervoltage lockout set point, VUV 18 V
Overvoltage cutoff set point, VOV 33 V
Inrush current limit, IINRUSH 2.4 A
Maximum load current, IOUT 22 A
IEC61000-4-5 Surge test level ±500 V with 2-Ω generator impedance
Surge performance Class-A

3.2 Detailed Design Procedure

  • Device selection

    In this example, the TPS26631 variant is considered to highlight the current sharing during the 2 × pulse current support. For more information, see the Device Comparison Table in the TPS2663x 60-V, 6-A Power Limiting, Surge Protection Industrial eFuse data sheet for device selection. In a system where reverse current blocking is not required, the TPS1663 devices are recommended.

  • ILIM setting

    To limit the inrush current to 2.4 A (that is, 0.6 A per device), the RLIM_Low is selected as 30 kΩ. Considering the cumulative current limit accuracy of 10% and to support maximum load current of 22 A, the current limit is set at 24 A (that is, 6 A per device). This results in 3.33-kΩ value for RLIM_High.

  • Undervoltage Lockout and Overvoltage Set Point

    The resistors R1, R2, and R3 are selected as 887 kΩ, 29.4 kΩ, and 34 kΩ, respectively, to set 18 V as undervoltage lockout and 33 V as overvoltage trip point.

  • dVdT capacitor

    Leave dVdT pins OPEN because the RILIM resistor switch network is considered in this design.

  • IMON resistor

    In parallel configuration, IMON pins of all the devices can be combined to monitor the total system current. The maximum value of the RIMON resistor can be determined by Equation 1. The maximum VIMON voltage is determined by the ADC input range and it is 3.3 V.

    Equation 1.

    Where GAINIMON is 27.9 µA/A (typ) and IOUT_max is 48 A because of 2 × overcurrent pulse support with the TPS26631.

    Using Equation 1, we get RIMON as 2.46 kΩ.

  • PGOOD, FLTb

    The output of these pins are used only from the primary eFuse to control downstream load and these pins are left OPEN for the rest of the parallel TPS26631 devices.

  • PGTH

    The TPS2663 device uses PGTH as the output load voltage monitor and to set the downstream loads UVLO threshold. The voltage at PGTH determines the way the TPS2663 recovers during the system faults. During the fault recovery instance, if the V(PGTH) level is above V(PGTHF), then the internal FET turns ON with a fast slew rate to meet Class-A system performance during surge events with optimal output buffer capacitance.

    Typically, the minimum operating voltage of the DC-DC converter designed for 24-V rail is at 15 V. Assuming UVLO to be at 20% lower level, VUVLO_DC-DC = 12 V. Use Equation 2 to calculate R4 and R5.

    Equation 2.

    V(PGTHF) = 1.14 V. Assuming R5 = 56 kΩ, R4 comes out to be approximately 499 kΩ.

  • Output Buffer Capacitor, COUT

    During the surge event TSURGE, the output capacitor COUT of the TPS2663 provides energy to the load. The COUT should be selected such that the output voltage does not drop below VUVLO_DC-DC during TSURGE interval. Use Equation 3 to compute the required buffer capacitor COUT:

    Equation 3.

    where

    • P(DC-DC) = max load power ≈ 500 W
    • TSURGE ≈ 1 ms
    • V(IN_SYS) = 24 V
    • V(UV_DC-DC) = 15 V

    The value is determined to be COUT = 2.85 mF. Choose a capacitor with ±10% tolerance, COUT = 3 mF / 35 V electrolytic capacitor.

  • Input and output capacitors

    A minimum of 0.1-µF ceramic decoupling capacitor is recommended at the input and the output for each of the eFuse.

  • Reverse current blocking FET

    Choose at least a 80-V rated N-channel FET. Two CSD19532Q5B FETs are used in parallel to support continuous load current of 22 A.

  • TVS diode and Schottky diode

    For clamping ±500-V, 2-Ω surge voltages with in the absolute maximum voltage rating of the TPS2663 device, bidirectional TVS diode SMCJ36CA is used at the input. Similarly, to clamp the negative voltages at the output during fast turn-off events, a Schottky diode B560C-13-F is recommended at the output.

3.3 Performance Results

Figure 3-1 shows the PCB with four TPS26631 devices.

GUID-20201025-CA0I-HJJT-WMVK-FL0WNXRNBKVX-low.jpg Figure 3-1 Evaluation Board With Four TPS26631 Devices in Parallel
GUID-20201025-CA0I-B6SK-TW3X-Z3MPB69TTGFT-low.pngFigure 3-2 Turn-on Control With SHDN
GUID-20201025-CA0I-MK3G-ZVNX-NWSVXHLBTTXP-low.pngFigure 3-4 IMON Response During Load Current Step From 2 A to 20 A
GUID-20201025-CA0I-PN9X-JRRW-PSLMQ450KRWZ-low.pngFigure 3-6 Overload Performance During Load Current Step From 15 A to 28 A
GUID-20201025-CA0I-SJKL-LVKW-XZPSRHJDRPZQ-low.pngFigure 3-8 Response During Recovery From Overload Fault
GUID-20201025-CA0I-HBSC-DBQK-RLZVVVCHJHH1-low.pngFigure 3-10 Response During Recovery From Output Short-Circuit
GUID-20201025-CA0I-C22R-FJ6K-TL9B4S8QJV8X-low.pngFigure 3-12 Response During Hot-Short at the Output
Figure 3-14 Voltage Interruption Response of Four TPS26630 Devices in Parallel Configuration (POUT = 45 W; COUT = 3 mF)
Figure 3-16 –500-V, 2-Ω Surge Response of Four TPS26631 Devices in Parallel Configuration
GUID-20201025-CA0I-HDG9-GLWD-DTFWB0CBCZPB-low.pngFigure 3-3 Turn-off Control With SHDN
GUID-20201025-CA0I-T3V7-85GB-ZHGBWNXPDN7C-low.pngFigure 3-5 Current Sharing Between Two Devices During Load Current Step from 2 A to 20 A
GUID-20201025-CA0I-M2CZ-SZDD-ZWJSGXBZMN3Z-low.pngFigure 3-7 Current Sharing Between Two Devices During Overload Fault
GUID-20201025-CA0I-SMWM-BDHM-ZL4KMND0DZFM-low.pngFigure 3-9 Response During Start-up With Short on Output
GUID-20201025-CA0I-HNFV-85KW-68HPLH2QXNLN-low.pngFigure 3-11 Current Sharing Between Two Devices During Start-up With Short on Output
Figure 3-13 Mismatch (%) in Steady-State Current Sharing in a Four eFuse Parallel Configuration
Figure 3-15 500-V, 2-Ω Surge Response of Four TPS26631 Devices in Parallel Configuration

 

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