SLUAA80 November 2020 TPS40322
Figure 2-2 shows the FB network circuit.
Converter DC regulation forces VFB = VREF = 0.6 V. Therefore, the divider is injecting current iINJ into the FB node to offset the output voltage.
KCL at FB node:
Rearrange and simplify as Equation 2 shows:
KCL @ X to solve for Vx:
Rearrange and simplify as Equation 5 shows:
where Vx equals Equation 5.
These calculations are integrated in the TPS40322 Resistor Divider Vout Offset Calculator tool.