SLAZ545T July 2013 – May 2021 MSP430F5242
PMAP Module
Functional
Port Mapping Controller does not clear unselected inputs to mapped module.
The Port Mapping Controller provides the logical OR of all port mapped inputs to a module (Timer, USCI, etc). If the PSEL bit (PxSEL.y) of a port mapped input is cleared, then the logic level of that port mapped input is latched to the current logic level of the input. If the input is in a logical high state, then this high state is latched into the input of the logical OR. In this case, the input to the module is always a logical 1 regardless of the state of the selected input.
1. Drive input to the low state before clearing the PSEL bit of that input and switching to another input source.
or
2. Use the Port Mapping Controller reconfiguration feature, PMAPRECFG, to select inputs to a module and map only one input at a time.