SLAZ187T October   2012  – May 2021 MSP430F2617

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      ZQW113
      2.      PM64
      3.      PN80
      4.      ZCA113
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC25
    2. 6.2  BCL12
    3. 6.3  BCL13
    4. 6.4  BCL15
    5. 6.5  CPU8
    6. 6.6  CPU16
    7. 6.7  CPU19
    8. 6.8  DAC4
    9. 6.9  DMA3
    10. 6.10 DMA4
    11. 6.11 DMA13
    12. 6.12 FLASH19
    13. 6.13 FLASH24
    14. 6.14 FLASH25
    15. 6.15 FLASH27
    16. 6.16 FLASH36
    17. 6.17 JTAG23
    18. 6.18 PORT10
    19. 6.19 PORT12
    20. 6.20 TA12
    21. 6.21 TA16
    22. 6.22 TA21
    23. 6.23 TAB22
    24. 6.24 TB2
    25. 6.25 TB16
    26. 6.26 TB24
    27. 6.27 USCI20
    28. 6.28 USCI21
    29. 6.29 USCI22
    30. 6.30 USCI23
    31. 6.31 USCI24
    32. 6.32 USCI25
    33. 6.33 USCI26
    34. 6.34 USCI27
    35. 6.35 USCI30
    36. 6.36 USCI34
    37. 6.37 USCI35
    38. 6.38 USCI40
    39. 6.39 XOSC5
    40. 6.40 XOSC8
  7. 7Revision History

BCL12

BCL Module

Category

Functional

Function

Switching RSELx or modifying DCOCTL can cause DCO dead time or a complete DCO stop

Description

After switching RSELx bits (located in register BCSCTL1) from a value of >13 to a value of <12 OR from a value of <12 to a value of >13, the resulting clock delivered by the DCO can stop before the new clock frequency is applied. This dead time is approximately 20 us. In some instances, the DCO may completely stop, requiring a power cycle.

Furthermore, if all of the RSELx bits in the BSCTL1 register are set, modifying the DCOCTL register to change the DCOx or the MODx bits could also result in DCO dead time or DCO hang up.

Workaround

- When switching RSEL from >13 to <12, use an intermediate frequency step. The intermediate RSEL value should be 13.


GUID-20201119-CA0I-XBDP-MZKL-BHL9R3DNGZ9X-low.png


AND

- When switching RSEL from <12 to >13 it's recommended to set RSEL to its default value first (RSEL = 7) before switching to the desired target frequency.

AND
- In case RSEL is at 15 (highest setting) it's recommended to set RSEL to its default value first (RSEL = 7) before accessing DCOCTL to modify the DCOx and MODx bits. After the DCOCTL register modification the RSEL bits can be manipulated in an additional step.

In the majority of cases switching directly to intermediate RSEL steps as described above will prevent the occurrence of BCL12. However, a more reliable method can be implemented by changing the RSEL bits step by step in order to guarantee safe function without any dead time of the DCO.

Note that the 3-step clock startup sequence consisting of clearing DCOCTL, loading the BCSCTL1 target value, and finally loading the DCOCTL target value as suggested in the in the "TLV Structure" chapter of the MSP430x2xx Family User's Guide is not affected by BCL12 if (and only if) it is executed after a device reset (PUC) prior to any other modifications being made to BCSCTL1 since in this case RSEL still is at its default value of 7. However any further changes to the DCOx and MODx bits will require the consideration of the workaround outlined above.