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  • TPSM365R6 and TPSM365R3 Functional Safety FIT Rate, FMD and Pin FMA

    • SFFS534 October   2022 TPSM365R3 , TPSM365R6

       

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  • TPSM365R6 and TPSM365R3 Functional Safety FIT Rate, FMD and Pin FMA
  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 TPSM365R6
    2. 2.2 TPSM365R3
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)
  6. IMPORTANT NOTICE
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FUNCTIONAL SAFETY FIT RATE, FMD AND PIN-FMA

TPSM365R6 and TPSM365R3 Functional Safety FIT Rate, FMD and Pin FMA

Trademarks

All trademarks are the property of their respective owners.

1 Overview

This document contains information for TPSM365R6 and TPSM365R3 (VQFN-HR package) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and their distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

Figure 1-1 Functional Block Diagram

TPSM365R6 and TPSM365R3 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

ADVANCE INFORMATION for preproduction products; subject to change without notice.

2 Functional Safety Failure In Time (FIT) Rates

2.1 TPSM365R6

This section provides Functional Safety Failure In Time (FIT) rates for TPSM365R6 based on two different industry-wide used reliability standards:

  • Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
  • Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2
Table 2-1 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11
FIT IEC TR 62380 / ISO 26262FIT (Failures Per 109 Hours)
Total Component FIT Rate

29

Die FIT Rate

5

Package FIT Rate

24

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

  • Mission Profile: Motor Control from Table 11
  • Power dissipation: 600 mW
  • Climate type: World-wide Table 8
  • Package factor (lambda 3): Table 17b
  • Substrate Material: FR4
  • EOS FIT rate assumed: 0 FIT
Table 2-2 Component Failure Rates per Siemens Norm SN 29500-2
TableCategoryReference FIT RateReference Virtual TJ
5 CMOS/ BICMOS
ASICs Analog & Mixed HV > 50-V supply
30 FIT 75°C

The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

2.2 TPSM365R3

This section provides Functional Safety Failure In Time (FIT) rates for TPSM365R3 based on two different industry-wide used reliability standards:

  • Table 2-3 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
  • Table 2-4 provides FIT rates based on the Siemens Norm SN 29500-2
Table 2-3 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11
FIT IEC TR 62380 / ISO 26262FIT (Failures Per 109 Hours)
Total Component FIT Rate

29

Die FIT Rate5
Package FIT Rate24

The failure rate and mission profile information in Table 2-3 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

  • Mission Profile: Motor Control from Table 11
  • Power dissipation: 300 mW
  • Climate type: World-wide Table 8
  • Package factor (lambda 3): Table 17b
  • Substrate Material: FR4
  • EOS FIT rate assumed: 0 FIT
Table 2-4 Component Failure Rates per Siemens Norm SN 29500-2
TableCategoryReference FIT RateReference Virtual TJ
5 CMOS/ BICMOS
ASICs Analog & Mixed HV > 50-V supply
30 FIT 75°C

The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-4 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for TPSM365R6 and TPSM365R3 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
No Output Voltage

60%

Output not in specification - voltage or timing

30%

Power Good - False Trip or Failure to Trip

5%

Short Circuit any two pins

5%

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPSM365R6 and TPSM365R3. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the TPSM365R6 and TPSM365R3 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPSM365R6 and TPSM365R3 data sheet.

1. See the data sheet for more details. Pin 1 trimmed and factory-set for externally adjustable switching frequency RT variants only.
2. Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only.
3. Pin 9 trimmed and factory-set for fixed output voltage VOUT/BIAS variants only.
4. Pin 9 factory-set for adjustable output voltage FB variants only.
Figure 4-1 Pin Diagram
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
PGOOD1When not in use, this pin can be left open or grounded. However, PGOOD is no longer reliably relays Power-Good information to devices connected to this pin.

B

EN2VOUT = 0 V, device is disabled.

B

VIN3VOUT = 0 V.B
VOUT4Goes into hiccup, short-circuit operation.B
SW

5, 6

Damage occurs.A
BOOT

7

VOUT = 0 V, HS FET does not turn on.B
VCC

8

VOUT = 0 V.B
VOUT/BIAS or FB

9

VOUT = 0 V.B
GND10Normal operation.D
RT or MODE

11

For RT, the switching frequency is set to 2.2 MHz. For MODE/SYNC the device goes into PFM mode.B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
PGOOD

1

When not in use, this pin can be left open or grounded. However, PGOOD is no longer reliably relays Power-Good information to devices connected to this pin.

B
EN

2

VOUT behavior is not defined. VOUT may be 0V, but it also may be up. Do not float this pin. Device can no longer reliably be enabled or disabled by other devices connected to this pin.

B
VIN

3

VOUT = 0 V.B
VOUT4VOUT = 0 V.B
SW5, 6Normal operation.

D

BOOT

7

Normal operation.

D

VCC

8

VCC output is unstable, can increase above 5.5 VA
FB

9

VOUT = 0 V. Do not float this pin.

B

GND

10

VOUT can be abnormal, as reference voltage is not fixed.

B

RT or MODE

11

If it is RT device, then frequency is not defined. If it is a MODE/SYNC device, then the device can go back and forth between FPWM and PFM. VOUT is up, but only partially functional.

C
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.

Shorted to

Description of Potential Failure Effect(s)Failure Effect Class
PGOOD1

EN

If EN > 20 V, it damages devices connected to the PGOOD pin. A
EN2

VIN

VOUT normal (enable is on, all other blocks work). However, the device can no longer be disabled.

B
VIN3VOUTIf VIN >16 V, damage occurs.A
VOUT

4

SWDamage occurs.A
SW6

BOOT

VOUT = 0 V, HS does not turn on, no Cboot.B
BOOT7

VCC

Damage occurs to VCC LDO. The VCC LDO could no longer supply voltage to internal control circuits.A
VCC8

FB

Can be partially nonfunctional, no damage occurs.B
FB9

GND

VOUT = 0 V (for fixed option) switches at maximum duty cycle for ADJ option.B
GND10

RT or MODE

For RT, Switching Frequency is set to 2.2 MHz. For MODE/SYNC the device goes into PFM mode.

B

RT or MODE

11

PGOOD

If PGOOD is high and < 5.5 V, then Fsw = 1 MHz for RT, and is in FPWM mode for MODE/SYNC; If PGOOD is low, then Fsw = 2.2 MHz for RT, and PFM mode for RT. PGOOD absmax being 20 V, RT ESD damages if PG goes to 20 V.

A

Table 4-5 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
PGOOD

1

If VIN > 20 V, it damages PGOOD. PGOOD is no longer reliably relays Power-Good information to devices connected to this pin.A
EN

2

VOUT normal (enable is on, all other blocks work). However, the device can no longer be disabled.B
VIN

3

Normal operation.

D
VOUT4Damage occurs, if VIN > 16 V.A
SW

5, 6

Damage occurs.

A
BOOT

7

Damage occurs, the BOOT ESD clamp is damaged.A
VCC

8

If Vin > 5.5 V, damage occurs.A
FB

9

If VIN > 20 V, damage occurs.A
GND10VOUT = 0 V.

A

RT

11

If Vin > 5.5 V, damage occurs. If Vin < 5.5 V, switching frequency is 1 MHz.

A

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