All trademarks are the property of their respective owners.
This document contains information for TPSM365R6 and TPSM365R3 (VQFN-HR package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
TPSM365R6 and TPSM365R3 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
ADVANCE INFORMATION for preproduction products; subject to change without notice.
This section provides Functional Safety Failure In Time (FIT) rates for TPSM365R6 based on two different industry-wide used reliability standards:
| FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
|---|---|
| Total Component FIT Rate | 29 |
| Die FIT Rate | 5 |
| Package FIT Rate | 24 |
The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
| Table | Category | Reference FIT Rate | Reference Virtual TJ |
|---|---|---|---|
| 5 | CMOS/
BICMOS ASICs Analog & Mixed HV > 50-V supply |
30 FIT | 75°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
This section provides Functional Safety Failure In Time (FIT) rates for TPSM365R3 based on two different industry-wide used reliability standards:
| FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
|---|---|
| Total Component FIT Rate | 29 |
| Die FIT Rate | 5 |
| Package FIT Rate | 24 |
The failure rate and mission profile information in Table 2-3 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:
| Table | Category | Reference FIT Rate | Reference Virtual TJ |
|---|---|---|---|
| 5 | CMOS/
BICMOS ASICs Analog & Mixed HV > 50-V supply |
30 FIT | 75°C |
The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-4 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for TPSM365R6 and TPSM365R3 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| No Output Voltage | 60% |
| Output not in specification - voltage or timing | 30% |
| Power Good - False Trip or Failure to Trip | 5% |
Short Circuit any two pins | 5% |
This section provides a Failure Mode Analysis (FMA) for the pins of the TPSM365R6 and TPSM365R3. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TPSM365R6 and TPSM365R3 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPSM365R6 and TPSM365R3 data sheet.
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | When not in use, this pin can be left open or grounded. However, PGOOD is no longer reliably relays Power-Good information to devices connected to this pin. | B |
| EN | 2 | VOUT = 0 V, device is disabled. | B |
| VIN | 3 | VOUT = 0 V. | B |
| VOUT | 4 | Goes into hiccup, short-circuit operation. | B |
| SW | 5, 6 | Damage occurs. | A |
| BOOT | 7 | VOUT = 0 V, HS FET does not turn on. | B |
| VCC | 8 | VOUT = 0 V. | B |
| VOUT/BIAS or FB | 9 | VOUT = 0 V. | B |
| GND | 10 | Normal operation. | D |
| RT or MODE | 11 | For RT, the switching frequency is set to 2.2 MHz. For MODE/SYNC the device goes into PFM mode. | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | When not in use, this pin can be left open or grounded. However, PGOOD is no longer reliably relays Power-Good information to devices connected to this pin. | B |
| EN | 2 | VOUT behavior is not defined. VOUT may be 0V, but it also may be up. Do not float this pin. Device can no longer reliably be enabled or disabled by other devices connected to this pin. | B |
| VIN | 3 | VOUT = 0 V. | B |
| VOUT | 4 | VOUT = 0 V. | B |
| SW | 5, 6 | Normal operation. | D |
| BOOT | 7 | Normal operation. | D |
| VCC | 8 | VCC output is unstable, can increase above 5.5 V | A |
| FB | 9 | VOUT = 0 V. Do not float this pin. | B |
| GND | 10 | VOUT can be abnormal, as reference voltage is not fixed. | B |
RT or MODE | 11 | If it is RT device, then frequency is not defined. If it is a MODE/SYNC device, then the device can go back and forth between FPWM and PFM. VOUT is up, but only partially functional. | C |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| PGOOD | 1 | EN | If EN > 20 V, it damages devices connected to the PGOOD pin. | A |
| EN | 2 | VIN | VOUT normal (enable is on, all other blocks work). However, the device can no longer be disabled. | B |
| VIN | 3 | VOUT | If VIN >16 V, damage occurs. | A |
| VOUT | 4 | SW | Damage occurs. | A |
| SW | 6 | BOOT | VOUT = 0 V, HS does not turn on, no Cboot. | B |
| BOOT | 7 | VCC | Damage occurs to VCC LDO. The VCC LDO could no longer supply voltage to internal control circuits. | A |
| VCC | 8 | FB | Can be partially nonfunctional, no damage occurs. | B |
| FB | 9 | GND | VOUT = 0 V (for fixed option) switches at maximum duty cycle for ADJ option. | B |
| GND | 10 | RT or MODE | For RT, Switching Frequency is set to 2.2 MHz. For MODE/SYNC the device goes into PFM mode. | B |
RT or MODE | 11 | PGOOD | If PGOOD is high and < 5.5 V, then Fsw = 1 MHz for RT, and is in FPWM mode for MODE/SYNC; If PGOOD is low, then Fsw = 2.2 MHz for RT, and PFM mode for RT. PGOOD absmax being 20 V, RT ESD damages if PG goes to 20 V. | A |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| PGOOD | 1 | If VIN > 20 V, it damages PGOOD. PGOOD is no longer reliably relays Power-Good information to devices connected to this pin. | A |
| EN | 2 | VOUT normal (enable is on, all other blocks work). However, the device can no longer be disabled. | B |
| VIN | 3 | Normal operation. | D |
| VOUT | 4 | Damage occurs, if VIN > 16 V. | A |
| SW | 5, 6 | Damage occurs. | A |
| BOOT | 7 | Damage occurs, the BOOT ESD clamp is damaged. | A |
| VCC | 8 | If Vin > 5.5 V, damage occurs. | A |
| FB | 9 | If VIN > 20 V, damage occurs. | A |
| GND | 10 | VOUT = 0 V. | A |
RT | 11 | If Vin > 5.5 V, damage occurs. If Vin < 5.5 V, switching frequency is 1 MHz. | A |
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
