ZHCSER5 December   2015 UCD3138064A

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Options
    1. 3.1 Device Comparison Table
    2. 3.2 Product Selection Matrix
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 PMBus/SMBus/I2C Timing
    8. 5.8 Parametric Measurement Information
    9. 5.9 Typical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
    4. 6.4 Feature Description
      1. 6.4.1  System Module
        1. 6.4.1.1 Address Decoder (DEC)
        2. 6.4.1.2 Memory Management Controller (MMC)
        3. 6.4.1.3 System Management (SYS)
        4. 6.4.1.4 Central Interrupt Module (CIM)
      2. 6.4.2  Peripherals
        1. 6.4.2.1 Digital Power Peripherals
          1. 6.4.2.1.1 Front End
          2. 6.4.2.1.2 DPWM Module
          3. 6.4.2.1.3 DPWM Events
          4. 6.4.2.1.4 High Resolution DPWM
          5. 6.4.2.1.5 Over Sampling
          6. 6.4.2.1.6 DPWM Interrupt Generation
          7. 6.4.2.1.7 DPWM Interrupt Scaling/Range
      3. 6.4.3  Synchronous Rectifier Dead Time Optimization Peripheral
      4. 6.4.4  Automatic Mode Switching
        1. 6.4.4.1 Phase Shifted Full Bridge Example
        2. 6.4.4.2 LLC Example
        3. 6.4.4.3 Mechanism For Automatic Mode Switching
      5. 6.4.5  DPWMC, Edge Generation, IntraMux
      6. 6.4.6  Filter
        1. 6.4.6.1 Loop Multiplexer
        2. 6.4.6.2 Fault Multiplexer
      7. 6.4.7  Communication Ports
        1. 6.4.7.1 SCI (UART) Serial Communication Interface
        2. 6.4.7.2 PMBUS/I2C
        3. 6.4.7.3 SPI
      8. 6.4.8  Timers
        1. 6.4.8.1 24-Bit Timer
        2. 6.4.8.2 16-Bit PWM Timers
        3. 6.4.8.3 Watchdog Timer
      9. 6.4.9  General Purpose ADC12
      10. 6.4.10 Miscellaneous Analog
      11. 6.4.11 Brownout
      12. 6.4.12 Global I/O
      13. 6.4.13 Temperature Sensor Control
      14. 6.4.14 I/O Mux Control
      15. 6.4.15 Current Sharing Control
      16. 6.4.16 Temperature Reference
    5. 6.5 Device Functional Modes
      1. 6.5.1 DPWM Modes Of Operation
        1. 6.5.1.1 Normal Mode
        2. 6.5.1.2 Phase Shifting
        3. 6.5.1.3 DPWM Multiple Output Mode
        4. 6.5.1.4 DPWM Resonant Mode
      2. 6.5.2 Triangular Mode
      3. 6.5.3 Leading Edge Mode
    6. 6.6 Memory
      1. 6.6.1 Register Maps
        1. 6.6.1.1 CPU Memory Map and Interrupts
          1. 6.6.1.1.1 Memory Map (After Reset Operation)
          2. 6.6.1.1.2 Memory Map (Normal Operation)
          3. 6.6.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 6.6.1.2 Boot ROM
        3. 6.6.1.3 Customer Boot Program
        4. 6.6.1.4 Flash Management
        5. 6.6.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
          1. 7.2.2.2.1 DPWM Synchronization
        3. 7.2.2.3 Fixed Signals to Bridge
        4. 7.2.2.4 Dynamic Signals to Bridge
        5. 7.2.2.5 System Initialization for PCM
          1. 7.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.5.2 Peak Current Detection
          3. 7.2.2.5.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 IC Grounding and Layout Guidelines
        2. 7.2.5.2 Layout Example
  8. 8器件和文档支持
    1. 8.1 器件支持
    2. 8.2 文档支持
      1. 8.2.1 相关文档
    3. 8.3 社区资源
    4. 8.4 商标
    5. 8.5 静电放电警告
    6. 8.6 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
V33D V33D to DGND –0.3 3.8 V
V33DIO V33DIO to DGND –0.3 3.8 V
V33A V33A to AGND –0.3 3.8 V
BP18 BP18 to DGND –0.3 2.5 V
Ground difference |DGND – AGND| 0.3 V
All Pins, excluding AGND (2) Voltage applied to any pin –0.3 3.8 V
Junction Temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommend Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V33D Digital power 3 3.3 3.6 V
V33DIO Digital I/O power 3 3.3 3.6 V
V33A Analog power 3 3.3 3.6 V
BP18 1.8-V digital power 1.6 1.8 2 V
TJ Junction temperature –40 - 125 °C

5.4 Thermal Information

THERMAL METRIC (1) UCD3138064A UNIT
VQFN (RGC) VQFN (RGZ) WQFN (RMH)
64 PINS 48 PINS 40 PINS
RθJA Junction-to-ambient thermal resistance 19.9 26.9 30.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 5.7 12.5 15.7 °C/W
RθJB Junction-to-board thermal resistance 3.1 3.9 5.7 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 3 4 5.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3 0.5 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.5 Electrical Characteristics

V33A = V33D = V33DIO = 3V to 3.6 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I33A Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA
I33DIO All GPIO and communication pins are open 0.35 mA
I33D ROM program execution 60 mA
I33D (4) Flash programming in ROM mode 70 mA
I33 The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded. 105 mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
EAP – EAN Error voltage digital resolution AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30 mV
AFE = 1 3.55 4 4.45 mV
AFE = 0 6.90 8 9.10 mV
R​EA (4) Input impedance (See Figure 6-2) AGND reference 0.5
IOFFSET Input offset current (See Figure 6-2) –5 5 μA
EADC Offset Input voltage = 0 V at AFE = 0 –2 2 LSB
Input voltage = 0 V at AFE = 1 –2.5 2.5 LSB
Input voltage = 0 V at AFE = 2 –3 3 LSB
Input voltage = 0 V at AFE = 3 –4 4 LSB
Sample Rate 15.625 MHz
Analog Front End Amplifier Bandwidth (4) 100 MHz
A0 Gain See Figure 6-3 1 V/V
Minimum output voltage 21 mV
EADC DAC
DAC range 0 1.6 V
VREF DAC reference resolution 10-bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4-bit dithering enabled 97.6 μV
INL –2.0 2.0 LSB
DNL –2.0 2.0 LSB
DAC reference voltage 1.58 1.61 V
ADC12
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage –40 to 125 °C 2.475 2.500 2.53 V
Change in Internal ADC reference from 25°C reference voltage (4) –40 to 25 °C –0.3 mV
25 to 125 °C –3.4
ADC12 INL integral nonlinearity, end point (4) ADC_SAMPLING_SEL = 6 for all ADC12 data, 25 to 125 °C -3.9 –2/+2 4.5 LSB
ADC12 INL integral nonlinearity, best fit -2.4 -1.5/+1.5 2.9 LSB
ADC12 DNL differential nonlinearity (4) –0.8/+2.9 LSB
ADC Zero Scale Error –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias 2.5 V applied to pin 200 nA
Input leakage resistance (4) ADC_SAMPLING_SEL= 6 or 0 1
Input Capacitance (4) 10 pF
ADC single sample conversion time 3.744 μs
DIGITAL INPUTS/OUTPUTS (1)
VOL Low-level output voltage (2) IOH = 4 mA, V33DIO = 3 V DGND
+ 0.25
V
VOH High-level output voltage (2) IOH = –4 mA, V33DIO = 3 V V33DIO – 0.6 V
VIH High-level input voltage V33DIO = 3 V 2.1 V
VIL Low-level input voltage V33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
VOL(PMBus) Low-level output voltage for PMBus pins (PMBUS_CLK, PMBUS_DATA, PMBUS_ALERT, PMBUS_CTRL) IOL = 20mA 400 mV
SYSTEM PERFORMANCE
tWD Watchdog timeout resolution 13.1 17 22.7 ms
Processor master clock (MCLK) 31.25 MHz
tDelay Digital filter delay (3) (1 clock = 32 ns) 6 MCLKs
Retention period of flash content (data retention and program) TJ = 25 °C 100 years
f(PCLK) Internal oscillator frequency 240 250 260 MHz
f(LFO) Internal low frequency oscillator frequency 10 MHz
Flash Read 1 MCLKs
ISHARE Current share current source (See Figure 6-25) 238 259 μA
RSHARE Current share resistor (See Figure 6-25) 9.75 10.3
POWER ON RESET AND BROWN OUT (V33A PIN, SEE Figure 5-4)
VGH Voltage Good High 2.6 V
VGL Voltage Good Low 2.55 V
Vres  (4) Voltage at which IReset signal is valid(4) 0.8 V
Brownout Internal signal warning of brownout conditions 2.9 V
TEMPERATURE SENSOR (4)
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution Volts/°C 5.9 mV/ºC
Temperature resolution Degree C per bit 0.1034 ºC/LSB
Accuracy (4) (5) –40 to 125 °C –10 ±5 10 ºC
Temperature range –40 to 125 °C –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
VAMB Ambient temperature Trimmed 25 °C reading 1.85 V
ANALOG COMPARATOR
DAC Reference DAC Range 0.01953 2.5 V
Reference Voltage 2.478 2.5 2.513 V
Bits 7 bits
INL (4) –0.5 0.21 LSB
DNL (4) 0.06 0.12 LSB
Offset (4) –19.5 19.5 mV
Reference DAC buffered output load (6) –0.5 1 mA
Buffer Offset (–0.5 mA) 0.156V < DAC < 2.363V -10 10 mV
Buffer Offset (1.0 mA) 0.059V < DAC < 2.305V -10 10 mV
(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset. During power up or power down, all GPIO pins output low.
(2) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
(3) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
(4) Characterized by design and not production tested.
(5) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(6) Available from reference DACs for comparators D, E, F and G.

5.6 Timing Characteristics

V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40 to 125 °C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
EADC DAC
τ Settling Time From 10 to 90% 250 ns
ADC12
ADC single sample conversion time (1) ADC_SAMPLING_SEL= 6 or 0 3.9 μs
SYSTEM PERFORMANCE
Time to disable DPWM output based on active FAULT pin signal High level on FAULT pin 70 ns
Retention period of flash content (data retention and program) TJ = 25 °C 100 years
Program time to erase one page or block in data flash or program flash 20 ms
Program time to write one word in data flash or program flash 30 µs
Sync-in/sync-out pulse width Sync pin 256 ns
Flash Write 20 μs
POWER ON RESET AND BROWN OUT (V33D PIN, SEE Figure 5-4
tPOR Time delay after Power is good or RESET* relinquished 1 ms
tEXC1 The time it takes from the device to exit a reset state and begin executing program flash bank 1 (32 kB). (1) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 9.5 ms
tEXC2 The time it takes from the device to exit a reset state and begin executing program flash bank 2 (32 kB). (1) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 19 ms
tEXCT The time it takes from the device to exit a reset state and begin executing the total program flash (64 kB). (1) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 19 ms
TEMPERATURE SENSOR (1)
tON Turn on time / settling time of sensor 100 μs
ANALOG COMPARATOR
Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator. (1) 150 ns
(1) Characterized by design and not production tested.

5.7 PMBus/SMBus/I2C Timing

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 5-1, Figure 5-1, and Figure 5-2. The numbers in Table 5-1 shows that the device supports standard (100 kHz), fast (400 kHz), and fast-mode plus (1 MHz) speeds.

Table 5-1 I2C/SMBus/PMBus Timing Characteristics

PARAMETER TEST CONDITIONS 100 kHz Class 400 kHz Class 1 MHz Class UNIT
MIN MAX MIN MAX MIN MAX
Typical values at TA = 25 °C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 10 400 10 1000 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 10 100 10 400 10 1000 kHz
t(BUF) Bus free time between start and stop(1) 4.7 1.3 0.5 µs
t(HD:STA) Hold time after (repeated) start(1) 4 0.6 0.26 µs
t(SU:STA) Repeated start setup time(1) 4.7 0.6 0.26 µs
t(SU:STO) Stop setup time(1) 4 0.6 0.26 µs
t(HD:DAT) Data hold time Receive mode 0 0 0 ns
t(SU:DAT) Data setup time 250 100 50 ns
t(TIMEOUT) Error signal/detect(2) 25 35 25 35 25 35 ms
t(LOW) Clock low period 4.7 1.3 0.5 µs
t(HIGH) Clock high period(3) 4 50 0.6 50 0.26 50 µs
t(LOW:SEXT) Cumulative clock low slave extend time(4) 25 25 25 ms
tr Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) 20
+ 0.1 Cb(5)
300 20
+ 0.1 Cb(5)
300 20
+ 0.1 Cb(5)
120 ns
tf Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) 20
+ 0.1 Cb(5)
1000 20
+ 0.1 Cb(5)
300 20
+ 0.1 Cb(5)
120 ns
Cb Total capacitance of one bus line 400 pF
(1) Fast mode, 400 kHz
(2) The device times out when any clock low exceeds t(TIMEOUT).
(3) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(4) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Cb (pF)
UCD3138064A I2C_tim_dia_lusap2.gif Figure 5-1 I2C/SMBus/PMBus Timing Diagram
UCD3138064A bus_timing_lusap2.gif Figure 5-2 Bus Timing in Extended Mode

5.8 Parametric Measurement Information

UCD3138064A Best_Fit_INL_End_Point_INL_slusc66.gif Figure 5-3 Best Fit INL and End Point INL
UCD3138064A POR_dwg_lusap2.gif Figure 5-4 Power On Reset (POR) / Brown Out Reset (BOR)
VGH This is the V33A threshold where the internal power is declared good. The UCD3138064A comes out of reset when above this threshold.
VGL This is the V33A threshold where the internal power is declared bad. The device goes into reset when below this threshold.
Vres This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state.
IReset This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC low.
TPOR The time delay from when VGH is exceeded to when the device comes out of reset.
Brown Out This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be triggered if enabled.

5.9 Typical Characteristics

(Data is taken from the UCD3138)

UCD3138064A G005a_SLUSBL8.gif Figure 5-5 EADC LSB Size with 4X Gain (mV) vs Temperature
UCD3138064A G003b_SLUSBL8.gif Figure 5-7 ADC12 2.5-V Reference vs Temperature
UCD3138064A G004c_SLUSBL8.gif Figure 5-9 Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs Temperature
UCD3138064A G006b_SLUSBL8.gif Figure 5-6 ADC12 Measurement Temperature Sensor Voltage vs Temperature
UCD3138064A G002b_SLUSBL8.gif Figure 5-8 ADC12 Temperature Sensor Measurement Error vs Temperature
UCD3138064A UCD3138064_clock_gating_pwer_savings3_SLUSB72.gif Figure 5-10 Clock Gating Power Savings

The power disable control register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.