ZHCSLD2E may   2020  – july 2023 UCC28782

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 描述
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Detailed Pin Description
      1. 8.3.1  BUR Pin (Programmable Burst Mode)
      2. 8.3.2  FB Pin (Feedback Pin)
      3. 8.3.3  REF Pin (Internal 5-V Bias)
      4. 8.3.4  VDD Pin (Device Bias Supply)
      5. 8.3.5  P13 and SWS Pins
      6. 8.3.6  S13 Pin
      7. 8.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 8.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 8.3.9  PWMH and AGND Pins
      10. 8.3.10 PWML and PGND Pins
      11. 8.3.11 SET Pin
      12. 8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 8.3.14 BIN, BSW, and BGND Pins
      15. 8.3.15 XCD Pin
      16. 8.3.16 CS, VS, and FLT Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 8.4.2  Dead-Time Optimization
      3. 8.4.3  EMI Dither and Dither Fading Function
      4. 8.4.4  Control Law across Entire Load Range
      5. 8.4.5  Adaptive Amplitude Modulation (AAM)
      6. 8.4.6  Adaptive Burst Mode (ABM)
      7. 8.4.7  Low Power Mode (LPM)
      8. 8.4.8  First Standby Power Mode (SBP1)
      9. 8.4.9  Second Standby Power Mode (SBP2)
      10. 8.4.10 Startup Sequence
      11. 8.4.11 Survival Mode of VDD (INT_STOP)
      12. 8.4.12 Capacitor Voltage Balancing Function
      13. 8.4.13 Device Functional Modes for Bias Regulator Control
        1. 8.4.13.1 Mitigation of Switching Interaction with ACF Converter
        2. 8.4.13.2 Protection Functions for the Bias Regulator
        3. 8.4.13.3 BIN-Pin Related Protections
        4. 8.4.13.4 BSW-Pin Related Protections
      14. 8.4.14 System Fault Protections
        1. 8.4.14.1  Brown-In and Brown-Out
        2. 8.4.14.2  Output Over-Voltage Protection (OVP)
        3. 8.4.14.3  Input Over Voltage Protection (IOVP)
        4. 8.4.14.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 8.4.14.5  Over-Temperature Protection (OTP) on CS Pin
        6. 8.4.14.6  Programmable Over-Power Protection (OPP)
        7. 8.4.14.7  Peak Power Limit (PPL)
        8. 8.4.14.8  Output Short-Circuit Protection (SCP)
        9. 8.4.14.9  Over-Current Protection (OCP)
        10. 8.4.14.10 External Shutdown
        11. 8.4.14.11 Internal Thermal Shutdown
      15. 8.4.15 Pin Open/Short Protections
        1. 8.4.15.1 Protections on CS pin Fault
        2. 8.4.15.2 Protections on P13 pin Fault
        3. 8.4.15.3 Protections on RDM and RTZ pin Faults
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Circuit
      1. 9.2.1 Design Requirements for a 65-W USB-PD Adapter Application
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 9.2.2.2 Transformer Calculations
          1. 9.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 9.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 9.2.2.2.3 Primary Winding Turns (NP)
          4. 9.2.2.2.4 Secondary Winding Turns (NS)
          5. 9.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 9.2.2.2.6 Winding and Magnetic Core Materials
        3. 9.2.2.3 Clamp Capacitor Calculation
          1. 9.2.2.3.1 Primary-Resonance ACF
          2. 9.2.2.3.2 Secondary-Resonance ACF
        4. 9.2.2.4 Bleed-Resistor Calculation
        5. 9.2.2.5 Output Filter Calculation
        6. 9.2.2.6 Calculation of ZVS Sensing Network
        7. 9.2.2.7 Calculation of BUR Pin Resistances
        8. 9.2.2.8 Calculation of Compensation Network
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  General Considerations
      2. 11.1.2  RDM and RTZ Pins
      3. 11.1.3  SWS Pin
      4. 11.1.4  VS Pin
      5. 11.1.5  BUR Pin
      6. 11.1.6  FB Pin
      7. 11.1.7  CS Pin
      8. 11.1.8  BIN Pin
      9. 11.1.9  BSW Pin
      10. 11.1.10 AGND Pin
      11. 11.1.11 BGND Pin
      12. 11.1.12 PGND Pin
      13. 11.1.13 EP Thermal Pad
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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订购信息

Survival Mode of VDD (INT_STOP)

When an output voltage overshoot occurs during step-down load transients, the VO feedback loop commands the UCC28782 to stop switching quickly by increasing IFB, in order to prevent additional energy from aggravating the overshoot. Since VVDD drops during this time, the typical way to prevent a controller from shutting down is to oversize the VDD capacitor (CVDD) so as to hold VVDD above VVDD(OFF). Instead, UCC28782 is equipped with survival-mode operation to hold VVDD above VVDD(OFF) during a transient event. Therefore, the size of CVDD can be significantly reduced and the PCB footprint for the auxiliary power can be minimized. Specifically, there is a ripple comparator to regulate VVDD above a 13-V threshold, which is VVDD(OFF) plus VVDD(PCT) in the electrical table. The ripple regulator is enabled when the VO feedback loop requests the UCC28782 to stop switching due to VO overshoot.

The regulator initiates unlimited PWML pulses when VVDD drops lower than 13 V, and stops switching after VVDD rises above 13 V. Since VVDD or VBIN is lower than the reflected output voltage overshoot, most of the magnetizing energy is delivered to the auxiliary winding and brings VBIN above 2.2 V or VVDD above 13 V quickly. After VO moves back to the regulation level, VO feedback loop forces the UCC28782 to begin switching again by reducing IFB, and the PWML and PWMH pulses are then controlled by the normal operating mode.

To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival mode at zero load, some guidelines on the auxiliary power delivery path to VDD should be considered:

  1. For fixed output voltage applications where the switching bias regulator is not required, the normal VVDD level under regulated VO must be designed to be above the 13-V threshold by an appropriate turns count for the auxiliary winding.
  2. CVDD should not be over-sized, but designed just large enough to hold VVDD > VVDD(OFF) under the longest VO soft-start time.
  3. For variable output voltage applications where the bias regulator is used, CVDD voltage can be ramped up faster if the turns count of the auxiliary winding (NAUX) can be increased, because the switching bias regulator can process more energy from its input, especially under the lowest output voltage condition. The design limitation on NAUX is the maximum voltage rating of BIN and BSW pins under the highest output voltage condition.
  4. The BIN-pin capacitor (CBIN) provides energy storage for the bias regulator. Higher CBIN value, such as >33 uF, can help avoid excess survival-mode operation and reduce the potential increase of VO under no-load conditions.
  5. When the bias regulator is not required, an auxiliary resistor in series with the auxiliary rectifier diode (DAUX) should not be too large of value, because the lower series impedance can help the VDD capacitor to charge faster.
  6. When the bias regulator is used, a series auxiliary resistor should not be used since it limits the energy transfer to CBIN. When the resistor is removed, one effective way to prevent CBIN from being overcharged by high leakage inductance or other potential energy source is to parallel a small 24-V TVS diode between the BIN pin and the AGND pin. If there is a layout limitation which forces the TVS diode connected to BGND pin instead, the impedance between BGND and AGND needs to be as small as possible, such that the TVS diode can clamp the voltage below the two pin ratings more effectively.
  7. If the output voltage dynamic range is very wide, such as from 3.3 V to 20 V, low auxiliary winding resistance less than 0.1 Ω and a Schottky-type auxiliary diode are recommended, such that the majority of the survival mode energy can be transferred to CBIN instead of diverting to the output capacitor under the lowest output voltage condition.
  8. Ensure good coupling between the auxiliary winding (NAUX) and the secondary winding (NS) of the transformer.

When the control loop is inevitably stuck in the survival mode at no load, it is important to ensure that the high-side switch can be responsive to the PWMH signal of the survival mode switching pattern entirely, such that the survival mode energy can be diverted to the boost converter and the risk of output voltage drifting higher than the regulation level can be mitigated. It is essential to choose the high-side driver with short power-on delay less than 10 μs.