ZHCSIB2B December   2017  – October 2019 UCC28064A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
      4. 8.3.4  Distortion Reduction
      5. 8.3.5  Zero-Current Detection and Valley Switching
      6. 8.3.6  Phase Management and Light-Load Operation
      7. 8.3.7  Burst Mode Operation
      8. 8.3.8  External Disable
      9. 8.3.9  Improved Error Amplifier
      10. 8.3.10 Soft Start
      11. 8.3.11 Brownout Protection
      12. 8.3.12 Line Dropout Detection
      13. 8.3.13 VREF
      14. 8.3.14 VCC
      15. 8.3.15 System Level Protections
        1. 8.3.15.1 Failsafe OVP - Output Over-voltage Protection
        2. 8.3.15.2 Overcurrent Protection
        3. 8.3.15.3 Open-Loop Protection
        4. 8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 8.3.15.5 Phase-Fail Protection
        6. 8.3.15.6 CS - Open, TSET - Open and Short Protection
        7. 8.3.15.7 Thermal Shutdown Protection
        8. 8.3.15.8 Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  ZCD Resistor Selection RZA, RZB
        4. 9.2.2.4  HVSEN
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Selecting RS For Peak Current Limiting
        7. 9.2.2.7  Power Semiconductor Selection (Q1, Q2, D1, D2)
        8. 9.2.2.8  Brownout Protection
        9. 9.2.2.9  Converter Timing
        10. 9.2.2.10 Programming VOUT
        11. 9.2.2.11 Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 9.2.3.2 Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Package Option Addendum
    1. 12.1 Packaging Information
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 开发支持
        1. 13.1.1.1 使用 WEBENCH® 工具创建定制设计
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Absolute Maximum Ratings

All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted.
MIN MAX UNIT
Continuous input voltage VCC(1) −0.5 21 V
COMP(2), PHB, HVSEN(3), VINAC(3), VSENSE(3), TSET, BRST –0.5 7
ZCDA, ZCDB –0.5 4
CS(4) –0.5 3
GDA, GDB(5) –0.5 VCC + 0.3
Continuous input current VCC 20 mA
ZCDA, ZCDB ±5
GDA, GDB(5) –25 25
VREF –2
Peak input current CS –30 mA
TJ Operating junction temperature –40 125 °C
TSOL Soldering 10 s 260 °C
Tstg Storage temperature –65 150 °C
(1) Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current limited below the absolute maximum continuous VCC input current level.
(2)  In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
(3) In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing. Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative voltage sources, and input currents as high as +0.5mA from positive voltage sources.
(4) In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these situations, negative voltage on CS may exceed the continuous absolute maximum rating.
(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to damp resonant ringing due to stray inductance.