11.1 Layout Guidelines

Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device operation and design robustness. The UCC27527 and UCC27528 family of gate drivers incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when designing with these high-speed drivers.

• Locate the driver device as close as possible to power device in order to minimize the length of high-current traces between the Output pins and the Gate of the power device.
• Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD during turn-on of power MOSFET. The use of low inductance SMD components such as chip resistors and chip capacitors is highly recommended.
• The turn-on and turn-off current loop paths (driver device, power MOSFET and VDD bypass capacitor) should be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is established in these loops at 2 instances – during turn-on and turn-off transients, which will induce significant voltage transients on the output pin of the driver device and Gate of the power MOSFET.
• Wherever possible parallel the source and return traces, taking advantage of flux cancellation
• Separate power traces and signal traces, such as output and input signals.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver should be connected to the other circuit nodes such as source of power MOSFET, ground of PWM controller etc at one, single point. The connected paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well
• In noisy environments, it may be necessary to tie inputs of an unused channel of UCC27527 to VDD (in case of INx+) or GND (in case of INX-) using short traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in the output.

11.2 Layout Example

Figure 34. Layout Example for UCC27528

Figure 35. Layout Example for UCC27527
(Channel A in Inverting and Channel B in Non-Inverting Configuration)

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a gate driver device to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC27527 and UCC27528 family of drivers is available in two different packages to cover a range of application requirements. The thermal metrics for each of these packages are summarized in the Thermal Information section of the datasheet. For detailed information regarding the thermal information table, please refer to Application Note from Texas Instruments entitled IC Package Thermal Metrics, SPRA953).

Among the different package options available in the UCC2752x family, of particular mention is the DSD package when it comes to power dissipation capability. The 3-mm x 3-mm WSON (DSD) package offer a means of removing the heat from the semiconductor junction through the exposed thermal pad at the base of the package. This pad is soldered to the copper on the printed circuit board directly underneath the device package, reducing the thermal resistance to a very low value. This allows a significant improvement in heat-sinking over that available in the D package. The printed circuit board must be designed with thermal lands and thermal vias to complete the heat removal subsystem. Note that the exposed pads in the WSON-8 package is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate of the device which is the ground of the device. It is recommended to externally connect the exposed pads to GND in PCB layout for better EMI immunity.