ZHCSFM4B september   2016  – december 2021 UCC21521

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programmable Dead Time
    5. 7.5 Powerup UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21521
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Gate to Source Resistor Selection
        5. 9.2.2.5 Estimate Gate Driver Power Loss
        6. 9.2.2.6 Estimating Junction Temperature
        7. 9.2.2.7 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.7.1 Selecting a VCCI Capacitor
          2. 9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.7.3 Select a VDDB Capacitor
        8. 9.2.2.8 Dead Time Setting Guidelines
        9. 9.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 静电放电警告
    8. 12.8 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V or 15V(1), 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRISEOutput rise time, 20% to 80% measured pointsCOUT = 1.8 nF 616ns
tFALLOutput fall time, 90% to 10% measured pointsCOUT = 1.8 nF712ns
tPWminMinimum pulse widthOutput off for less than minimum, COUT = 0 pF20ns
tPDHLPropagation delay from INx to OUTx falling edges1930ns
tPDLHPropagation delay from INx to OUTx rising edges1930ns
tPWDPulse width distortion |tPDLH – tPDHL|6ns
tDMPropagation delays matching between VOUTA, VOUTBf = 100 kHz5ns
tVCCI+ to OUTVCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB (See Figure 7-5 )INA or INB tied to VCCI40us
tVDD+ to OUTVDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB (See Figure 7-6)INA or INB tied to VCCI50100us
|CMH|High-level common-mode transient immunityINA and INB both are tied to VCCI;

VCM=1500 V; (See CMTI Testing.)

100V/ns
|CML|Low-level common-mode transient immunityINA and INB both are tied to GND;

VCM=1500 V; (See CMTI Testing.)

100
(1) VDDA=VDDB = 12 V is used for the test condition of 5 V and 8V UVLO, and VDDA=VDDB=15 V is used for 12-V UVLO.