ZHCSD29A November   2014  – November 2014 TVB1440

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Equalization
      2. 8.3.2 Configurable Output
      3. 8.3.3 Squelch
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Shutdown Mode
      3. 8.4.3 Squelch Mode
    5. 8.5 Programming
      1. 8.5.1 Local I2C Interface
      2. 8.5.2 Receiver (IN[3:0]P/N) Adjustments
        1. 8.5.2.1 Equalization Level
        2. 8.5.2.2 Squelch Level
      3. 8.5.3 Main Link Output [OUT[3:0]P/N] Adjustments
        1. 8.5.3.1 LINK Address Space
      4. 8.5.4 Example Script
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Common 4k2k TV Panel Configuration
          2. 9.1.1.2.2 1Max Stream Rate
          3. 9.1.1.2.3 Encoded Stream Rate
          4. 9.1.1.2.4 TVB1440 Configuration
          5. 9.1.1.2.5 Receiver Equalization Setting
          6. 9.1.1.2.6 Transmitter Settings
          7. 9.1.1.2.7 RESET
  10. 10Power Supply Recommendations
    1. 10.1 Power-Up Sequence
    2. 10.2 Power-Down Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Differential Pairs
      2. 11.1.2 Layout Example
      3. 11.1.3 Placement
      4. 11.1.4 Package Specific
      5. 11.1.5 Ground
  12. 12器件和文档支持
    1. 12.1 商标
    2. 12.2 静电放电警告
    3. 12.3 Export Control Notice
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VCC –0.3 4 V
VDD –0.3 1.3
Voltage range HS Link I/O (OUTx, INx) Differential Voltage –0.3 1.3 V
RSTN –0.3 1.3
SCL_CTL, SDA_CTL, ADDR, EN –0.3 4
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
TSTG Storage temperature range -65 150 ·C
Electrostatic discharge Human body model (HBM)(1) –2000 2000 V
Charged-device model (CDM)(2) –500 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VCC Supply Voltage, IO 3 3.6 V
VDD Supply Voltage, CORE 1 1.26 V
VIH High-level input voltage for ADDR, EN 1.9 3.6 V
VIL Low-level input voltage for ADDR, EN 0 0.8 V
VIH,RSTN High-level input voltage for RSTN (typical hysteresis of 80mV) 0.75 V
VIL,RSTN Low-level input voltage for RSTN (typical hysteresis of 80mV) 0.3 V
TA Operating free-air temperature 0 85 °C
fscl I2C CK frequency at SCL_CTL (standard I2C mode(1)) 100 kHz
(1) The local interface through SCL_CTL and SDA_CTL should follow standard mode I2C specifications

7.4 Thermal Information

THERMAL METRIC(1) TVB1440 UNIT
RGZ (48 Pin)
RθJA Junction-to-ambient thermal resistance 35.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 21.5
RθJB Junction-to-board thermal resistance 11.7
ψJT Junction-to-top characterization parameter 1.2
ψJB Junction-to-board characterization parameter 11.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
ICC Supply current 4 lanes operation(1) 130 230 mA
ISTDN Shutdown supply current(1) 1.5 3 mA
IOD Squelch (output disable) supply current 35 50 mA
VOD0 Output differential voltage swing 238 340 442 mVpp
VOD1 357 510 663
VOD2 484 690 897
VOD3 700 1000 1300
PE0 Output pre-emphasis 0 dB
PE1 3
PE2 6
PE3 9
ROUT Driver output impedance 50 Ω
I(TXSHORT) Output pins short circuit current limit 50 mA
V(SQUELCH) Squelch threshold voltage for input signals (default) 80 mVpp
(1) Values are VDD supply measurements; VCC supply measurements are 5 mA (typical) and 8 mA (max), with zero current in shutdown mode.

7.6 Timing Requirements

MIN TYP MAX UNIT
tramp1 Time VDD must stable before VCC is applied 10 µS
tramp2 Time RSTN must remain asserted until VCC/VDD voltage has reached minimum recommended operation 100 µS
tramp3 Time device will be available for operation after a valid reset 400 mS

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
tPD Propagation delay time 300 ps
tsk1 Intra-pair output skew (Figure 1) 20 ps
tsk2 Inter-pair output skew (Figure 1) 100 ps
Δtjit Total peak-to-peak residual jitter
VOD0; PE0; EQ = 8dB; clean source; minimum input and output cabling; PRBS7 data pattern.		 15 ps
tsq_enter Squelch entry time
Time from a loss of valid input signal to ML output off		 10 120 µS
tsq_exit Squelch exit time
Time from valid input signal available while in squelch mode to ML outputs on		 1 µS
output_skew_slase51.pngFigure 1. Output Skew Definitions

7.8 Typical Characteristics

D001_SLASE51.gif
Figure 2. Typical EQ Gain Curves (simulations)
fig4_eye_diagram_slase51.png
Figure 4. 3.75-Gbps Input With 20 Inch Trace
fig6_eye_diagram_slase51.png
Figure 6. 5-Gbps Input with 20 Inches Trace
D002_SLASE51.gif
Figure 3. Jitter Performance with Optimal EQ Settings
fig5_eye_diagram_slase51.png
Figure 5. 3.75-Gbps Output with 20 Inch Input Trace and
8-dB EQ Setting
fig7_eye_diagram_slase51.png
Figure 7. 5-Gbps Output with 20 Inch Input Trace and
13-dB EQ Setting