ZHCSGM7A August 2017 – September 2017 TUSB212
PRODUCTION DATA.
TUSB213 supports 100 kHz I2C for device configuration, status readback and test purposes. This controller is enabled after SCL and SDA pins are sampled high shortly after de-assertion of RSTN. In this mode, the register as described in Table 2 can be accessed by I2C read/write transaction to 7-bit slave address 0x2C. It is necessary to set CFG_ACTIVE bit and reset it to zero after making changes to the EQ and DC Boost level registers to restart the state machine.
NOTE
All registers or fields in Table 2 which are not specifically mentioned are considered reserved. The default value of these reserved registers or fields must not be changed. It is suggested to perform a read-modify-write operation to maintain the default value of the reserved fields.
Offset | Bit(s) | Name | Type | Default | Description |
---|---|---|---|---|---|
0x01 | 6:4 | ACB_LVL | RW | XXX (Sampled from EQ pin at reset) | Sets the level of AC Boost 000 : Level 0 AC Boost programmed [MIN] 001 : Level 1 AC Boost programmed 011 : Level 2 AC Boost programmed 111 : Level 3 AC Boost programmed [MAX] |
0x03 | 0 | CFG_ACTIVE | RW | 1b | Configuration mode 0 : Normal mode. State machine enabled. 1 : Configuration mode: State machine disabled. After reset, if I2C mode is true (SCL and SDA are both pulled high) it is maintained until it is cleared by an I2C write, but, if I2C mode is not true, it is cleared automatically. |
0x0E | 2:0 | DCB_LVL | RW | XXX (Sampled from DC_BOOST pin at reset) | Sets the level of DC Boost 011 : 40mV (DC_Boost = L) 101 : 60mV (DC_Boost = M, default) 111 : 80mV (DC_Boost = H) |