ZHCSGO4A August   2017  – September 2017 TPS7A88-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Voltage Regulation Features
        1. 7.3.1.1 DC Regulation
        2. 7.3.1.2 AC and Transient Response
      2. 7.3.2 System Start-Up Features
        1. 7.3.2.1 Programmable Soft-Start (NR/SSx)
        2. 7.3.2.2 Sequencing
          1. 7.3.2.2.1 Enable (ENx)
          2. 7.3.2.2.2 Undervoltage Lockout (UVLOx) Control
          3. 7.3.2.2.3 Active Discharge
        3. 7.3.2.3 Power-Good Output (PGx)
      3. 7.3.3 Internal Protection Features
        1. 7.3.3.1 Foldback Current Limit (ICLx)
        2. 7.3.3.2 Thermal Protection (Tsdx)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Regulation
      2. 7.4.2 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection
        1. 8.1.1.1 Setting the Output Voltage (Adjustable Operation)
        2. 8.1.1.2 Capacitor Recommendations
        3. 8.1.1.3 Input and Output Capacitor (CINx and COUTx)
        4. 8.1.1.4 Feedforward Capacitor (CFFx)
        5. 8.1.1.5 Noise-Reduction and Soft-Start Capacitor (CNR/SSx)
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Circuit Soft-Start Control (NR/SSx)
          1. 8.1.2.1.1 In-Rush Current
        2. 8.1.2.2 Undervoltage Lockout (UVLOx) Control
        3. 8.1.2.3 Power-Good (PGx) Function
      3. 8.1.3 AC and Transient Performance
        1. 8.1.3.1 Power-Supply Rejection Ratio (PSRR)
        2. 8.1.3.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 8.1.3.3 Output Voltage Noise
        4. 8.1.3.4 Optimizing Noise and PSRR
          1. 8.1.3.4.1 Charge Pump Noise
        5. 8.1.3.5 Load Transient Response
      4. 8.1.4 DC Performance
        1. 8.1.4.1 Output Voltage Accuracy (VOUTx)
        2. 8.1.4.2 Dropout Voltage (VDO)
          1. 8.1.4.2.1 Behavior When Transitioning From Dropout Into Regulation
      5. 8.1.5 Reverse Current Protection
      6. 8.1.6 Power Dissipation (PD)
        1. 8.1.6.1 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
        2. 11.1.1.2 Spice 模型
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RTJ|20
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance.

10.1.1 Board Layout

To maximize the AC performance of the TPS7A88-Q1, TI recommends following the layout example shown in Figure 59.This layout isolates the analog ground (AGND) from the noisy power ground. Components that must be connected to the quiet analog ground are the noise reduction capacitors (CNR/SSx) and the lower feedback resistors (R2 and R4). These components must have a separate connection back to the power pad of the device. To minimize crosstalk between the two outputs, the output capacitor grounds are positioned on opposite sides of the layout and only connect back to the device at opposite sides of the thermal pad. TI recommends connecting the GND pins directly to the thermal pad and not to any external plane.

To maximize the output voltage accuracy, the connection from each output voltage back to top output divider resistors (R1 and R3) must be made as close as possible to the load. This method of connecting the feedback trace eliminates the voltage drop from the device output to the load.

To improve thermal performance, a thermal via array must connect the thermal pad to internal ground planes. A larger area for the internal ground planes improves the thermal performance and lowers the operating temperature of the device.

10.2 Layout Example

TPS7A88-Q1 layout_sbvs248.gif Figure 59. TPS7A88-Q1 Example Layout