SLVSA76G March   2010  – January 2016 TPS65180B , TPS65181 , TPS65181B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Data Transmission Timing
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Modes of Operation
      2. 9.3.2 Mode Transisitons
      3. 9.3.3 Wake-Up and Power Up Sequencing
      4. 9.3.4 GPIO Control
      5. 9.3.5 I2C Control
    4. 9.4 Device Functional Modes
      1. 9.4.1 The FIX_RD_PTR Bit
    5. 9.5 Register Maps
      1. 9.5.1  Thermistor Readout (TMST_VALUE) Register (Offset = 0x00h)
      2. 9.5.2  Enable (ENABLE) Register (Offset = 0x01h)
      3. 9.5.3  Positive Voltage Rail Adjustment (VP_ADJUST) Register (Offset = 0x02h)
      4. 9.5.4  Negative Voltage Rail Adjustment (VN_ADJUST) Register (Offset = 0x03h)
      5. 9.5.5  VCOM Adjustment (VCOM_ADJUST) Register (Offset = 0x04h)
      6. 9.5.6  Interrupt Enable 1 (INT_ENABLE1) Register (Offset = 0x05h)
      7. 9.5.7  Interrupt Enable 2 (INT_ENABLE2) Register (Offset = 0x06h)
      8. 9.5.8  Interrupt INT_STATUS1 (INT_STATUS1) Register (Offset = 0x07h)
      9. 9.5.9  Interrupt Status 2 (INT_STATUS2) Register (Offset = 0x08h)
      10. 9.5.10 Power Sequence Register 0 (PWR_SEQ0) Register (Offset = 0x09h)
      11. 9.5.11 Power Sequence Register 1 (PWR_SEQ1) Register (Offset = 0x0Ah)
      12. 9.5.12 Power Sequence Register 2 (PWR_SEQ2) Register (Offset = 0x0Bh)
      13. 9.5.13 Thermistor Configuration Register (TMST_CONFIG) (Offset = 0x0Ch)
      14. 9.5.14 Thermistor Hot Threshold (TMST_OS) Register (Offset = 0x0Dh)
      15. 9.5.15 Thermistor Cool Threshold (TMST_HYST) Register (Offset = 0x0Eh)
      16. 9.5.16 Power-Good Status (PG_STATUS) Register (Offset = 0x0Fh)
      17. 9.5.17 Revision and Version Control (REVID) Register (Offset = 0x10h)
      18. 9.5.18 I2C Read Pointer Control (FIX_READ_POINTER) Register (Offset = 0x11h) (TPS65181 and TPS65181B ONLY)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1  Dependencies Between Rails
      2. 10.1.2  Soft-Start
      3. 10.1.3  VCOM Adjustment
      4. 10.1.4  VCOM Adjustment Through Register Control
      5. 10.1.5  VCOM Adjustment Through External Potentiometer
      6. 10.1.6  VPOS and VNEG Supply Tracking
      7. 10.1.7  Fault Handling and Recovery
      8. 10.1.8  TPS65180 and TPS65180B Fault Handling
      9. 10.1.9  TPS65181 and TPS65181B Fault Handling
      10. 10.1.10 Power-Good Pin
      11. 10.1.11 Interrupt Pin
      12. 10.1.12 Panel Temperature Monitoring
      13. 10.1.13 NTC Bias Circuit
      14. 10.1.14 TPS65180 and TPS65180B Temperature Acquisition
      15. 10.1.15 TPS65181 and TPS65181B Temperature Acquisition
      16. 10.1.16 Overtemperature Reporting
      17. 10.1.17 Overtemperature Fault Queuing
      18. 10.1.18 TPS65181 and TPS65181B Temperature Sensor
      19. 10.1.19 I2C Bus Operation
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9 Detailed Description

9.1 Overview

The TPS6518x and TPS65181xB family of devices provides two adjustable LDOs, inverting buck-boost converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. The system can be supplied by a regulated input voltage ranging from 3 V to 6 V. The device is characterized across a –10°C to 85°C temperature range, best suited for personal electronic applications.

The I2C interface provides comprehensive features for using the TPS6518x and TPS65181xB family of devices. All rails can be enabled or disabled. Power-up and power-down sequences can also be programmed through the I2C interface, as well as thermistor and interrupt configurations. Voltage adjustment can also be controlled by the I2C interface. The adjustable LDOs can supply up to 120 mA of current. The default output voltages for each LDO can be adjusted through the I2C interface. LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be less than 50 mV.

There are two charge pumps: VDDH and VEE 10 mA and 12 mA respectively. These charge pumps boost the DC-DC boost converters ±16-V rails to provide a gate channel supply. The power-good functionality is open-drain output, if any of the four power rails (CP1, CP2, LDO1, LDO2) are not in regulation, encounters a fault, or is disabled the pin is pulled low. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to Hi-Z state (pulled up by external resistor).

The TPS6518x and TPS65181xB family of devices provides circuitry to bias and measure an external NTC to monitor the display panel temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. Temperature measurements are triggered by the controlling host and the last temperature reading is always stored in the TMST_VALUE register.

Interrupts are issued when the temperature exceeds the programmable HOT, or drops below the programmable COLD threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value.

9.2 Functional Block Diagram

TPS65180 TPS65181 TPS65180B TPS65181B fbd_lvsa76.gif

9.3 Feature Description

9.3.1 Modes of Operation

The TPS6518x and TPS65181xB have three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode one or more power rails are enabled.

    SLEEP

    This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to default values and the device does not respond to I2C communications. TPS6518x and TPS65181xB enter SLEEP mode whenever WAKEUP pin is pulled low.

    STANDBY

    In STANDBY all internal support circuitry is powered up and the device is ready to accept commands either through GPIO or I2C control but none of the power rails are enabled. To enter STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be pulled low or the STANDBY bit of the ENABLE register must be set high. The device also enters STANDBY mode if input undervoltage lockout (UVLO), positive boost undervoltage (VB_UV), or inverting buck-boost undervoltage (VN_UV) is detected, or thermal shutdown occurs.

    ACTIVE

    The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is the normal mode of operation while the device is powered up. In ACTIVE mode, a falling edge on any PWRx pin shuts down and a rising edge powers up the corresponding rail.

9.3.2 Mode Transisitons

    SLEEP → ACTIVE

    WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in the order defined by the PWR_SEQx registers.

    SLEEP → STANDBY

    WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails remain down until one or more PWRx pin is pulled high.

    ACTIVE → SLEEP

    WAKEUP pin is pulled low (falling edge). Rails are shut down in the reverse power-up order defined by PWR_SEQ registers.

    ACTIVE → STANDBY

    WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), undervoltage lockout (UVLO), positive boost or inverting buck-boost undervoltage (UV), or when STANDBY bit is set to 1, the device shuts down all rails in the reverse power-up order defined by the PWR_SEQx registers.

    STANDBY → ACTIVE

    WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the same order as PWRx pins are pulled high. Alternatively, if ACTIVE bit is set to 1, output rails power up in the order defined by the PWR_SEQx registers.

    STANDBY → SLEEP

    WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled.

TPS65180 TPS65181 TPS65180B TPS65181B global_state4_lvsa76.gif Figure 3. Global State Diagram

9.3.3 Wake-Up and Power Up Sequencing

The TPS6518x and TPS65181xB support flexible power-up sequencing through GPIO control using the PWR3, 2, 1, 0 pins or I2C control using the PWR_SEQ0, 1, 2 registers. Using GPIO control, the output rails are enabled/disabled in the order in which the PWRx pins are asserted or de-asserted, respectively, and the power-up timing is controlled by the host only.

In I2C control mode the power-up and power-down order and timing are defined by user register settings. The default settings support the E Ink Vizplex panel and typically do not need to be charged by the user.

9.3.4 GPIO Control

Under GPIO control the system host in E Ink Vizplex panel module enables the TPS6518x and TPS65181xB output rails by asserting the PWR0, PWR1, PWR2, PWR3 signals and the host has full control over the order and timing in which the output rails are powered up and down. Rails are in regulation 2 ms after their respective PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power up. The additional time is needed to power up the positive and inverting buck-boost regulator which need to be turned on before any other rail can be enabled. When all rails are enabled and in regulation the PWR_GOOD pin is released
(pin status = Hi-Z and power-good line is pulled high by external pullup resistor). The PWRx pins are assigned to the rails as follows:

  • PWR0: LDO2 (VNEG) and VCOM
  • PWR1: CP2 (VEE)
  • PWR2: LDO2 (VPOS)
  • PWR3: CP1 (VDDH)

Rails are powered down whenever the host de-asserts the respective PWRx pin, and when all rails are disabled the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode which is the lowest-power mode of operation.

It is possible for the host to force the TPS6518x and TPS65181xB directly into SLEEP mode from ACTIVE mode by de-asserting the WAKEUP pin in which case the device follows the power-down sequence defined by the PWR_SEQx registers before entering SLEEP mode.

9.3.5 I2C Control

Under I2C control the power-up sequence is defined by the PWR_SEQx registers rather than through GPIO control. In SLEEP mode the TPS6518x and TPS65181xB are completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high while all PWRx pins are held low and the device enters STANDBY mode which enables the I2C interface. Write to the PWR_SEQ0 register to define the order in which the output rails is enabled at power-up and to the PWR_SEQ1 and PWR_SEQ2 registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails.

It is possible for the host to force the TPS6518x and TPS65181xB directly into ACTIVE mode from SLEEP mode by pulling the WAKEUP pin high while at least one of the PWRx pins is pulled high. In this case the default power-up sequence defined by the PWR_SEQx registers applies and the device starts powering up the rails 5.5 ms after the WAKEUP signal has been pulled high.

To power-down the device, set the STANDBY bit of the ENABLE register to 1 then the TPS6518x and TPS65181xB follows the reverse power-up sequence to bring down all power rails. While the sequencer is busy powering up the power rails, any activity on the PWRx pins is ignored. When all rails are up, any of the output rails can be disabled by applying a negative edge on the PWRx input pins, that is, if the host toggles the PWRx pin high-low or low-high-low, the respective rail is disabled regardless of how it has been enabled.

TPS65180 TPS65181 TPS65180B TPS65181B i2c_ctrl_lvsa76.gif Figure 4. I2C Control

9.4 Device Functional Modes

9.4.1 The FIX_RD_PTR Bit

The TPS65181 and TPS65181B devices support a special I2C mode, making them compatible with the EPSON Broadsheet S1D13521 timing controller. Standard I2C protocol requires the following steps to read data from a register:

  1. Send device slave address, R/nW bit set low (write command)
  2. Send register address
  3. Send device slave address, R/nW set high (read command)
  4. The slave responds with data from the specified register address.

The EPSON Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed registers (step 1. and 2. above) but needs to access the temperature data from the TPS65181 or TPS65181B TMST_VALUE register. To support Broadsheet based systems, the TPS65181 and TPS65181B automatically trigger temperature acquisition every 60s and stores the result in TMST_VALUE register. With the FIX_RD_PTR bit in the FIX_RD_POINTER register set to 1 the device responds to any I2C read command with data from the TMST_VALUE register. No write command with the register address is required and address auto increment feature is disabled in this mode. Therefore reading the temperature data is reduced to two steps:

  1. Send device address, R/nW set high (read command)
  2. Read the data from the slave. The slave responds with data from TMST_VALUE register address.

Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the TPS65180 and TPS65180B with two exceptions:

  1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can read any register different from the TMST_VALUE register.
  2. Thermal Shutdown (TSD), positive boost undervoltage (VB_UV), inverting buck-boost undervoltage (VN_UV), and input undervoltage lockout (UVLO) interrupt bits do not have to be cleared before output rails can be re-enabled.

At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit and the display controller can start accessing the temperature information. During normal operation the main controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit must be written 0.

9.5 Register Maps

Table 1. Register Address Map

REGISTER ADDRESS (HEX) NAME DEFAULT
VALUE		 DESCRIPTION
0 0x00 TMST_VALUE N/A Thermistor value read by ADC
1 0x01 ENABLE 0001 1111 Enable/disable bits for regulators
2 0x02 VP_ADJUST 0010 0011 Voltage settings for VPOS, VDDH
3 0x03 VN_ADJUST 1010 0011 Voltage settings for VNEG, VEE
4 0x04 VCOM_ADJUST 0111 0100 Voltage settings for VCOM
5 0x05 INT_ENABLE1 0111 0100 Interrupt enable group1
6 0x06 INT_ENABLE2 1111 1011 Interrupt enable group2
7 0x07 INT_STATUS1 0xxx xx00 Interrupt status group1
8 0x08 INT_STATUS2 xxxx x0xx Interrupt status group2
9 0x09 PWR_SEQ0 1110 0100 Power up sequence
10 0x0A PWR_SEQ1 0010 0010 DLY0, DLY1 time set
11 0x0B PWR_SEQ2 0010 0010 DLY2, DLY3 time set
12 0x0C TMST_CONFIG 0010 0000 Thermistor configuration
13 0x0D TMST_OS 0011 0010 Thermistor hot temp set
14 0x0E TMST_HYST 0010 1101 Thermistor cool temp set
15 0x0F PG_STATUS 0000 0000 Power-good status each rails
16 0x10 REVID 0100 0001 Device revision ID information
17 0x11 FIX_READ_POINTER 0000 0000 I2C read pointer control

9.5.1 Thermistor Readout (TMST_VALUE) Register (Offset = 0x00h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME TMST_VALUE[7:0]
READ/WRITE R R R R R R R R
RESET VALUE N/A N/A N/A N/A N/A N/A N/A N/A
FIELD NAME BIT DEFINITION
TMST_VALUE[7:0] Temperature read-out
1111 0110 – < -10°C
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1 °C
0000 0000 – 0 °C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0101 0101 – 85°C
0101 0101 – > 85°C

9.5.2 Enable (ENABLE) Register (Offset = 0x01h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME ACTIVE STANDBY V3P3_SW
_EN		 VCOM_EN VDDH_EN VPOS_EN VEE_EN VNEG_EN
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 0 1 1 1 1 1
FIELD NAME BIT DEFINITION(1)
ACTIVE STANDBY to ACTIVE transition bit
1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by PWR_SEQx registers.
0 – No effect
NOTE: After transition bit is cleared automatically.
STANDBY ACTIVE to STANDBY transition bit
1 – Transition from ACTIVE to STANDBY mode. Rails power down as defined by PWR_SEQx registers.
0 – No effect
NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE.
V3P3_SW_EN VIN3P3 to V3P3 switch enable
1 – Switch is ON
0 – Switch id OFF
VCOM_EN VCOM buffer enable
1 – Enabled
0 – Disabled
VDDH_EN VDDH charge pump enable
1 – Enabled
0 – Disabled
VPOS_EN VPOS LDO regulator enable
1 – Enabled
0 – Disabled
NOTE: VPOS cannot be enabled before VNEG is enabled.
VEE_EN VEE charge pump enable
1 – Enabled
0 – Disabled
VNEG_EN VNEG LDO regulator enable
1 – Enabled
0 – Disabled
NOTE: When VNEG is disabled VPOS is also disabled.
(1) Enable/disable bits for regulators are AND’d with PWRx signals.

9.5.3 Positive Voltage Rail Adjustment (VP_ADJUST) Register (Offset = 0x02h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME Not used VDDH_SET[2:0] not used VPOS_SET[2:0]
READ/WRITE R R/W R/W R/W R R/W R/W R/W
RESET VALUE 0 0 1 0 0 0 1 1
FIELD NAME BIT DEFINITION(1)
Not used N/A
VDDH_SET[2:0] VDDH voltage setting
000 – VDDH increase by 10%
001 – VDDH increase by 5%
010 – Nominal
011 – VDDH decrease by 5%
100 – VDDH decrease by 10%
101 – Reserved
110 – Reserved
111 – Reserved
Not used N/A
VPOS_SET[2:0] VPOS voltage setting
000 : |VNEG| - 0.75 V
001 : |VNEG| - 0.5 V
010 : |VNEG| - 0.25 V
011 : |VNEG|
100 : |VNEG| + 0.25 V
101 : |VNEG| + 0.5 V
110 : |VNEG| + 0.75 V
111 – Reserved
NOTE: For proper tracking of the VPOS and VNEG supply these bits must remain set at their default value of 011b. VPOS tracks VNEG automatically when VNEG_SET[2:0] bits of VN_ADJUST register are changed.
(1) VDDH is decreased from set value defined by resistor divider. Decreased VDDH value must be within spec range.

9.5.4 Negative Voltage Rail Adjustment (VN_ADJUST) Register (Offset = 0x03h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VCOM_ADJ VEE_SET[2:0] Not used VNEG_SET[2:0]
READ/WRITE R/W R/W R/W R/W R R/W R/W R/W
RESET VALUE 1(1) 0 1 0 0 0 1 1
(1) TPS65180/TPS65180B: Bit defaults to 1; TPS65181/TPS65181B: Bit defaults to 0
FIELD NAME BIT DEFINITION
VCOM_ADJ VCOM output adjustment method
0 – VCOM_XADJ pin
1 – I2C interface
VEE_SET[2:0](1) VDDH voltage setting
000 – VEE decrease by 10%
001 – VEE decrease by 5%
010 – Nominal
011 – VEE increase by 5%
100 – VEE increase by 10%
101 – Reserved
110 – Reserved
111 – Reserved
not used N/A
VNEG_SET[2:0] VNEG voltage setting
000 – -15.75 V
001 – -15.50 V
010 – -15.25 V
011 – -15.00 V
100 – -14.75 V
101 – -14.50 V
110 – -14.25 V
111 – Reserved
(1) VEE is decreased from set value defined by resistor divider. Decreased VEE value must be within spec range.

9.5.5 VCOM Adjustment (VCOM_ADJUST) Register (Offset = 0x04h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VCOM_SET[7:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 1 1 1 0 1 0 0
FIELD NAME BIT DEFINITION
VCOM_SET[7:0] VCOM voltage adjustment
0000 0000 – 0 V
0000 0001 – 11 mV
0000 0010 – 22 mV
...
0111 0011 – 1239 mV
0111 0100 – 1250 mV
0111 0101 – 1261 mV
...
1111 1111 – 2750 mV
NOTE: step size is rounded to 11 mV. Theoretical step size is 2750 mV / 255 mV = 10.78 mV. Parametric performance is guranteed from -0.3 V to -2.5 V only.

9.5.6 Interrupt Enable 1 (INT_ENABLE1) Register (Offset = 0x05h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME Not used TSD_EN HOT_EN TMST_HOT
_EN		 TMST_COOL_EN UVLO_EN Not used Not used
READ/WRITE R R/W R/W R/W R/W R/W R R
RESET VALUE 0 1 1 1 0 1 0 0
FIELD NAME BIT DEFINITION
Not used N/A
TSD_EN Thermal shutdown interrupt enable
1 – Enabled
0 – Disabled
HOT_EN Thermal shutdown early warning enable
1 – Enabled
0 – Disabled
TMST_HOT_EN Thermistor hot warning enable
1 – Enabled
0 – Disabled
TMST_COOL_EN Thermistor hot escape interrupt enable
1 – Enabled
0 – Disabled
UVLO_EN VIN undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
Not used N/A
Not used N/A

9.5.7 Interrupt Enable 2 (INT_ENABLE2) Register (Offset = 0x06h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VB_UV_EN VDDH_UV
_EN		 VN_UV_EN VPOS_UV_EN VEE_UV
_EN		 not used VNEG_UV
_EN		 EOC_EN
READ/WRITE R/W R/W R/W R/W R/W R R/W R/W
RESET VALUE 1 1 1 1 1 0 1 1
FIELD NAME BIT DEFINITION
VB_UV_EN Positive boost converter undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
VDDH_UV_EN VDDH undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
VN_UV_EN Inverting buck-boost converter undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
VPOS_UV_EN VPOS undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
VEE_UV_EN VEE undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
not used N/A
VNEG_UV_EN VNEG undervoltage detect interrupt enable
1 – Enabled
0 – Disabled
EOC_EN ADC end of conversion interrupt enable
1 – Enabled
0 – Disabled

9.5.8 Interrupt INT_STATUS1 (INT_STATUS1) Register (Offset = 0x07h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME Not used TSDN HOT TMST_HOT TMST_COOL UVLO Not used Not used
READ/WRITE R R R R R R R R
RESET VALUE 0 N/A N/A N/A N/A N/A 0 0
FIELD NAME BIT DEFINITION
Not used N/A
TSD Thermal shutdown interrupt
HOT Thermal shutdown early warning
TMST_HOT Thermistor hot warning
TMST_COOL Thermistor hot escape interrupt
UVLO VIN undervoltage detect interrupt
Not used N/A
Not used N/A

9.5.9 Interrupt Status 2 (INT_STATUS2) Register (Offset = 0x08h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VB_UV VDDH_UV VN_UV VPOS_UV VEE_UV Not used VNEG_UV EOC
READ/WRITE R R R R R R R R
RESET VALUE N/A N/A N/A N/A N/A 0 N/A N/A
FIELD NAME BIT DEFINITION(1)
VB_UV Positive boost converter undervoltage detect interrupt
VDDH_UV VDDH undervoltage detect interrupt
VN_UV Inverting buck-boost converter undervoltage detect interrupt
VPOS_UV VPOS undervoltage detect interrupt
VEE_UV VEE undervoltage detect interrupt
not used N/A
VNEG_UV VNEG undervoltage detect interrupt
EOC ADC end of conversion interrupt
(1) Undervoltage detect bit is set if the corresponding rail does not come up 5 ms after it is enabled except for DCDC1 and 2 which are set 10 ms after they are enabled.

9.5.10 Power Sequence Register 0 (PWR_SEQ0) Register (Offset = 0x09h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VDDH_SEQ[1:0] VPOS_SEQ[1:0] VEE_SEQ[1:0] VNEG_SEQ[1:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 1 1 1 0 0 1 0 0
FIELD NAME BIT DEFINITION(1)
VDDH_SEQ[1:0] VDDH power-up/down order
00 – Power-up/down on STROBE1
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
VPOS_SEQ[1:0] VPOS power-up/down order
00 – Power-up/down on STROBE1
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Ppower-up/down on STROBE4
VEE_SEQ[1:0] VEE power-up/down order
00 – Power-up/down on STROBE1
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
VNEG_SEQ[1:0] VNEG power-up/down order
00 – Power-up/down on STROBE1
01 – Power-up/down on STROBE2
10 – Power-up/down on STROBE3
11 – Power-up/down on STROBE4
(1) Power-down sequence follows the reverse order of power-up.

9.5.11 Power Sequence Register 1 (PWR_SEQ1) Register (Offset = 0x0Ah)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME DLY1[3:0] DLY0[3:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 1 0 0 0 1 0
FIELD NAME BIT DEFINITION
DLY1[3:0] DLY1 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up and from STROBE2 to STROBE1 during power-down.
0000 – 0 ms
0001 – 1 ms
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
DLY0[3:0] DLY0 delay time set; defines the delay time from WAKEUP high to STROBE1 during power-up and from WAKEUP low to STROBE4 during power-down.
0000 – 0 ms
0001 – 1 ms
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms

9.5.12 Power Sequence Register 2 (PWR_SEQ2) Register (Offset = 0x0Bh)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME DLY3[3:0] DLY2[3:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 1 0 0 0 1 0
FIELD NAME BIT DEFINITION
DLY3[3:0] DLY3 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up and from STROBE4 to STROBE3 during power-down.
0000 – 0 ms
0001 – 1 ms
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms
DLY2[3:0] DLY2 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up and from STROBE3 to STROBE2 during power-down.
0000 – 0 ms
0001 – 1 ms
0010 – 2 ms
0011 – 3 ms
...
1110 – 14 ms
1111 – 15 ms

9.5.13 Thermistor Configuration Register (TMST_CONFIG) (Offset = 0x0Ch)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME READ_
THERM		 Not used CONV_END FAULT_QUE [1:0] FAULT_QUE
_CLR		 Not used Not used
READ/WRITE R/W R R R/W R/W R/W R R
RESET VALUE 0 0 1 0 0 0 0 0
FIELD NAME BIT DEFINITION
READ_THERM Read thermistor value
1 – Initiates temperature acquisition
0 – No effect
NOTE: bit is self-cleared after acquisition is completed
Not used N/A
CONV_END ADC conversion done flag
1 – Conversion is finished
0 – Conversion is not finished
FAULT_QUE [1:0] Number of faults to detect before TMST_HOT interrupt is asserted
00 – 1 time
01 – 2 times
10 – 4 times
11 – 6 times
FAULT_QUE_CLR Fault counter clear
1 – Clears fault counter
0 – Fault counter is cleared automatically if thermistor reading is less than TMST_HOT_SET[7:0]
Not used N/A
Not used N/A

9.5.14 Thermistor Hot Threshold (TMST_OS) Register (Offset = 0x0Dh)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME TMST_HOT_SET[7:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 1 1 0 0 1 0
FIELD NAME BIT DEFINITION
TMST_HOT_SET[7:0] Defined the thermistor HOT threshold
1000 0000 – Reserved
...
1111 0101 – Reserved
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1°C
0000 0000 – 0°C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0011 0010 – 50°C
...
0101 0101 – 85°C
0101 0110 – Reserved
...
0111 1111 – Reserved

9.5.15 Thermistor Cool Threshold (TMST_HYST) Register (Offset = 0x0Eh)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME TMST_COOL_SET[7:0]
READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0 0 1 0 1 1 0 1
FIELD NAME BIT DEFINITION
TMST_HOT_SET[7:0] Defined the thermistor HOT threshold
1000 0000 – Reserved
...
1111 0101 – Reserved
1111 0110 – -10°C
1111 0111 – -9°C
...
1111 1110 – -2°C
1111 1111 – -1°C
0000 0000 – 0°C
0000 0001 – 1°C
0000 0010 – 2°C
...
0001 1001 – 25°C
...
0010 1101 – 45°C
...
0101 0101 – 85°C
0101 0110 – Reserved
...
0111 1111 – Reserved

9.5.16 Power-Good Status (PG_STATUS) Register (Offset = 0x0Fh)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME VB_PG VDDH_PG VN_PG VPOS_PG VEE_PG Not used VNEG_PG Not used
READ/WRITE R R R R R R R R
RESET VALUE 0 0 0 0 0 0 0 0
FIELD NAME BIT DEFINITION
VB_PG Positive boost converter power-good
VDDH_PG VDDH power-good
VN_PG Inverting buck-boost power-good
VPOS_PG VPOS power-good
VEE_PG VEE power-good
not used N/A
VNEG_PG VNEG power-good
not used N/A

9.5.17 Revision and Version Control (REVID) Register (Offset = 0x10h)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME REVID[7:0]
READ/WRITE R R R R R R R R
RESET VALUE 0 1 1 1 0 0 0 0
FIELD NAME BIT DEFINITION
REVID [7:0] 0101 0000 - TPS65180 1p1
0110 0000 - TPS65180 1p2
0111 0000 - TPS65180B (TPS65180 1p3)
1000 0000 - TPS65180B (TPS65180 1p4)
0101 0001 - TPS65181 1p1
0110 0001 - TPS65181 1p2
0111 0001 - TPS65181B (TPS65181 1p3)
1000 0001 - TPS65181B (TPS65181 1p4)

9.5.18 I2C Read Pointer Control (FIX_READ_POINTER) Register (Offset = 0x11h) (TPS65181 and TPS65181B ONLY)

DATA BIT D7 D6 D5 D4 D3 D2 D1 D0
FIELD NAME Not used Not used Not used Not used Not used Not used Not used FIX_RD_PTR
READ/WRITE R R R R R R R R/W
RESET VALUE 0 0 0 0 0 0 0 0
FIELD NAME BIT DEFINITION
Not used N/A
Not used N/A
Not used N/A
Not used N/A
Not used N/A
Not used N/A
Not used N/A
FIX_RD_PTR I2C read pointer control
1 – Read pointer is fixed to 0x00
0 – read pointer is controlled through I2C