ZHCSG44E June 2017 – December 2022 TPS650864
PRODUCTION DATA
Programmable Power Good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3 pin reach their regulation range to Power Good assertion. This is an optional register as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|
Bit Name | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GPO3_PG_ DELAY[2] | GPO3_PG_ DELAY[1] | GPO3_PG_ DELAY[0] |
TPS6508640 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
TPS65086401 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
TPS6508641 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
TPS65086470 | 0 | 0 | 0 | 0 | 0 | — | — | — |
Access | R | R | R | R | R | R/W | R/W | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
2:0 | GPO3_PG_DELAY[2:0] | R/W | X | Programmable delay Power Good or level shifter for GPO3 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation. 000: 2.5 ms 001: 5.0 ms 010: 10 ms 011: 15 ms 100: 20 ms 101: 50 ms 110: 75 ms 111: 100 ms —: Bits not used. If GPO3 is controlled by I2C rather than PG and is not used internally for VTT LDO enable, these bits have no impact. Default is set to 0b. |