ZHCSI59I July 2009 – May 2018 TPS65070 , TPS65072 , TPS65073 , TPS650731 , TPS650732
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
DEFLDO2 | B7 | B6 | B5 | B4 | B3 | B2 | B1 | BO |
---|---|---|---|---|---|---|---|---|
Bit name and function | LDO2 tracking | LDO2[5] | LDO2[4] | LDO2[3] | LDO2[2] | LDO2[1] | LDO2[0] | |
Default for –70, –72 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
Default for –73, –731, –732 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 |
Default value loaded by: | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | UVLO | |
Read/write | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
The DEFLDO2 register is used to set the output voltage of LDO2 according to the voltage table defined under DEFDCDC3 when Bit LDO2 tracking is set to 0. In case Bit LDO2 tracking is set to 1, the output voltage of LDO2 is defined by the contents defined for DCDC3.
Bit 6 | LDO2 TRACKING:
0 = the output voltage is defined by register DEFLDO2 1 = the output voltage follows the setting defined for DCDC3 (DEFDCDC3_LOW or DEFDCDC3_HIGH, depending on the state of pin DEFDCDC3) |
Bit 5..0 | LDO2[5] to LDO2[0]:
output voltage setting for LDO2 similar to DCDC3 |