SLVS871D February   2010  – June 2016 TPS62660 , TPS62665

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dissipation Ratings
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Switching Frequency
      2. 8.3.2 Mode Selection
      3. 8.3.3 Enable
      4. 8.3.4 Soft Start
      5. 8.3.5 Output Capacitor Discharge
      6. 8.3.6 Undervoltage Lockout
      7. 8.3.7 Short-Circuit Protection
      8. 8.3.8 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Save Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Checking Loop Stability
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Voltage at VIN, SW(2) –0.3 7 V
Voltage at FB(2) –0.3 3.6 V
Voltage at EN, MODE (2) –0.3 VI + 0.3 V
IO Peak output current 1000 mA
Power dissipation Internally limited
TA Operating temperature(3) –40 85 °C
TJ (max) Maximum operating junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA(max)= TJ(max) – (RθJA × PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 105°C.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±1000
Machine model (MM) ±200
(1) The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VI Supply voltage 2.3 5.5 V
IOUT Maximum output current 1000 mA
Effective inductance 0.3 0.47 1.3 µH
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS626xx UNIT
YFF (DSBGA)
6 PINS
RθJA Junction-to-ambient thermal resistance 130 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.2 °C/W
RθJB Junction-to-board thermal resistance 22 °C/W
ψJT Junction-to-top characterization parameter 5 °C/W
ψJB Junction-to-board characterization parameter 22 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum values are at VI = 2.3 V to 5.5 V, VO = 1.8 V, EN = 1.8 V, AUTO mode and TA = –40°C to 85°C; circuit in the Parameter Measurement Information (unless otherwise noted). Typical values are at VI = 3.6 V, VO = 1.8 V, EN = 1.8 V, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VI Input voltage range 2.3 5.5 V
IQ Operating quiescent current IO = 0 mA. Device not switching 31 55 μA
IO = 0 mA, PWM mode 7.6 mA
I(SD) Shutdown current EN = GND 0.2 2.5 μA
UVLO Undervoltage lockout threshold 2.05 2.1 V
ENABLE, MODE
VIH High-level input voltage 1 V
VIL Low-level input voltage 0.4 V
Ilkg Input leakage current Input connected to GND or VIN 0.01 1 μA
POWER SWITCH
rDS(on) P-channel MOSFET ON-resistance TPS6266x VI = V(GS) = 3.6 V, PWM mode 270 mΩ
VI = V(GS) = 2.5 V, PWM mode 350
Ilkg P-channel leakage current, PMOS V(DS) = 5.5 V, –40°C ≤ TJ ≤ 85°C 1 μA
rDS(on) N-channel MOSFET ON-resistance TPS6266x VI = V(GS) = 3.6 V, PWM mode 140 mΩ
VI = V(GS) = 2.5 V, PWM mode 200
Ilkg N-channel leakage current, NMOS V(DS) = 5.5 V, –40°C ≤ TJ ≤ 85°C 2 μA
rDIS Discharge resistor for power-down sequence TPS62665 15 50 Ω
P-MOS current limit 2.3 V ≤ VI ≤ 4.8 V, open loop 1400 1500 1750 mA
Input current limit under short-circuit
conditions		 VO shorted to ground 19 mA
Thermal shutdown 140 °C
Thermal shutdown hysteresis 10 °C
OSCILLATOR
fSW Oscillator frequency TPS6266x IO = 0 mA, PWM mode 5.4 6 6.6 MHz
OUTPUT
V(OUT) Regulated DC output voltage TPS6266x 2.3 V ≤ VI ≤ 2.7 V, 0 mA ≤ IO ≤ 600 mA
2.7 V ≤ VI ≤ 3 V, 0 mA ≤ IO ≤ 800 mA
3 V ≤ VI ≤ 4.8 V, 0 mA ≤ IO ≤ 1000 mA
PFM/PWM operation		 0.98 × VNOM VNOM 1.03 × VNOM V
3 V ≤ VI ≤ 5.5 V, 0 mA ≤ IO ≤ 1000 mA
PFM/PWM operation		 0.98 × VNOM VNOM 1.04 × VNOM
2.3 V ≤ VI ≤ 2.7 V, 0 mA ≤ IO ≤ 600 mA
2.7 V ≤ VI ≤ 3 V, 0 mA ≤ IO ≤ 800 mA
3 V ≤ VI ≤ 5.5 V, 0 mA ≤ IO ≤ 1000 mA
PWM operation		 0.98 × VNOM VNOM 1.02 × VNOM
Line regulation VI = VO + 0.5 V (min 2.3 V) to 5.5 V, IO = 200 mA 0.13 %/V
Load regulation VI = 3.6 V, IO = 0 mA to 1000 mA –0.00025 %/mA
Feedback input resistance 480 kΩ
ΔVO Power-save mode ripple voltage TPS62660 IO = 1 mA 20 mVPP
TPS62661 IO = 1 mA
L = 1 μH (muRata LQM2MPN1R0NG0)
CO = 10 μF, 4 V 0402 (muRata GRM155R60G106M)		 9
TPS62665 IO = 1 mA 24
Start-up time TPS62660 IO = 0 mA, time from active EN to VO 120 μs
TPS62661 RL = 2 Ω, time from active EN to VO 55

6.6 Dissipation Ratings(1)

PACKAGE RθJA (2) RθJB (2) POWER RATING
TA ≤ 25°C		 DERATING FACTOR
ABOVE TA = 25°C
YFF-6 125°C/W 53°C/W 800 mW 8 mW/°C
(1) Maximum power dissipation is a function of TJ(max), RθJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = [TJ(max)-TA] / RθJA.
(2) This thermal data is measured with high-K board (4-layer board according to JESD51-7 JEDEC standard).

6.7 Typical Characteristics

Table 1. Table of Graphs

FIGURE
η Efficiency vs load current Figure 1, Figure 2, Figure 3, Figure 4
vs input voltage Figure 5
Peak-to-peak output ripple current vs load current Figure 6, Figure 7
TPS62660 TPS62665 eff3_io_lvs871.gif Figure 1. Efficiency vs Load Current
TPS62660 TPS62665 eff4_io_lvs871.gif Figure 3. Efficiency vs Load Current
TPS62660 TPS62665 eff_vi_lvs871.gif Figure 5. Efficiency vs Input Voltage
TPS62660 TPS62665 vo_io_lvs871.gif Figure 7. Peak-to-Peak Output Ripple Voltage vs Load Current
TPS62660 TPS62665 eff_io_lvs871.gif Figure 2. Efficiency vs Load Current
TPS62660 TPS62665 eff4b_io_lvs871.gif Figure 4. Efficiency vs Load Current
TPS62660 TPS62665 effb_vi_lvs871.gif Figure 6. Peak-to-Peak Output Ripple Voltage vs Load Current