7.3.1 Supply Voltage

The TPS61177A device has a built-in linear regulator to supply the device analog and logic circuit. The VCC pin is recommended to be open without any capacitance load. VCC does not have high current sourcing capability for external use and typically is regulated at 3.3 V.

7.3.2 Boost Regulator

The fixed-frequency PWM boost converter uses current-mode control and has integrated loop compensation. The internal compensation ensures stable output over the full input and output voltage ranges assuming the recommended inductance and output capacitance values shown in Figure 36. The output voltage of the boost regulator is automatically set by the device to minimize voltage drop across the CS pins. The device regulates the lowest CS pin to 500 mV at 20-mA current and consistently adjusts the boost output voltage to account for any changes in LED forward voltages. If the input voltage is higher than the sum of the WLED forward voltage drops (at low duty cycles), the boost converter is not able to regulate the output due to its minimum duty cycle limitation. In this case, increase the number of WLEDs in series or include series ballast resistors in order to provide enough headroom for the converter to boost the output voltage. Since the TPS61177A integrates a 1.8-A, 40-V power MOSFET, the boost converter can provide up to a 39-V output voltage.

7.3.3 Programmable Switch Frequency and Slew Rate

Both switching frequency and slew rate of TPS61177A can be programmable by a E²PROM register value which is pre-set before device power up. The switching frequency has four options adjustable to 450 kHz, 600 kHz, 800 kHz, or 1200 kHz. The slew rate of switching FET from off to on also has four selections: 1.3 V/ns, 2.5 V/ns, 3.5 V/ns to 4.6 V/ns.

See FREQ (A3h) and SR (A4h) for E²PROM address and data table of boost switching frequency programming and boost switching slew rate selection.

The adjustable switching frequency feature provides the user with the flexibility of choosing either a faster switching frequency by using an inductor with smaller inductance and footprint or a slower switching frequency to get potentially higher efficiency due to lower switching losses. In additional, the selectable slew rate for switching gives flexibility to trade off between switching loss and electronic-magnetic interference (EMI) effects to the application system.

7.3.4 LED Current Sinks

The six current sink regulators embedded in the TPS61177A can be collectively configured to provide up to a maximum of 30 mA each. These six specialized current sinks are accurate to within ±3% max for currents at 20 mA, with a string-to-string difference of ±2%.

Each CS channel current must be programmed to the highest WLED current expected; each CS channel current is programmable from 15 mA to 30 mA by an E²PROM register through the I²C interface. See CS (A1h) for the E²PROM register table of CS current programming.

7.3.5 Enable and Start-Up Timing

The internal regulator which provides VCC wakes up as soon as ENB is applied. VCC does not come to full regulation until VINB voltage is above UVLO. Before boost convert start-up, the TPS61177A checks the status of all current feedback channels and shuts down any unused feedback channels. It is recommended to short the unused channels to ground for faster start-up.

After the device is enabled, if the PWM pin is left floating or grounded, the output voltage of the TPS61177A regulates to the minimum output voltage. Once the device detects a voltage on the PWM pin, the TPS61177A begins to regulate the CS pin current, as a pre-set per the E²PROM register data, according to the duty cycle of the signal on the PWMB pin. The boost converter output voltage rises to the appropriate level to accommodate the sum of the white LED string with the highest forward voltage drops plus the headroom of the current sink at that current.

Pulling the ENB pin low shuts down the device, resulting in consumption of less than 10 µA in shutdown mode.

The TPS61177A also integrates power-up sequence control for start-up. There is no specified power or control signal sequence requirement for VINB, ENB, and PWMB. Figure 17 provides the detail timing diagram for TPS61177A start-up and shutdown.

Figure 17. Start-up and Shutdown Timing Diagram

The PWMB decoder delay time period is determined by different dimming mode, input duty cycle, and frequency on the PWMB pin. In PWM mode, the decoder delay time is zero. Once the rising edge is detected on the PWMB pin, the output voltage starts ramping up immediately. While in mixed dimming mode or analogdimming mode, the decoder delay time is equal to twice input PWM signal cycle time and 400 µs minimally. If PWM signal input keeps at high level after first rising edge, the decoder delay is about 20 ms.

Figure 18 provides the detail timing diagram for TPS61177A start-up and shutdown when one of CS channel is open. The VLED voltage always ramps up to the overvoltage protection threshold which is 39.5 V typically, if one of CS pin is floating. The device then detects the zero current string, and removes it from the feedback loop.

Figure 18. Start-Up and Shutdown Timing Diagram (Mixed Mode and DC Mode)

7.3.6 Input Undervoltage Protection (UVLO)

The TPS61177A will not start up until the VINB voltage is higher than the UVLO threshold which is preset by E²PROM register data. During normal operation, if the VINB drops below UVLO with 200-mV hysteresis, the TPS61177A immediately shuts down. See UVLO (A2h) for E²PROM address and data table of UVLO threshold.

7.3.7 Overvoltage Protection (OVP)

The TPS61177A integrates output OVP which is fixed at 39.5 V typically. Once the VLED pin detects the voltage higher than 39.5 V, the boost switching regulator stops switching until the voltage of VLED pin drop below 39.5 V with 500-mV hysteresis.

7.3.8 Current-Sink Open Protection

If one of the device WLED strings is open, the device automatically detects and disables that string. The open WLED string is detected by sensing no current in the corresponding CS pin. As a result, the TPS61177A deactivates the open current sink and removes it from the voltage feedback loop. Subsequently, the output voltage drops and is regulated to the minimum voltage required for the connected WLED strings. The CS currents of the connected WLED strings remain in regulation.

The device turns off if it detects that all of the WLED strings are open. If an open string is reconnected again, a power-on reset (POR) or ENB pin toggling is required to reactivate a previously deactivated string.

7.3.9 Overcurrent Protection

The TPS61177A has a pulse-by-pulse overcurrent limit of 1.8 A (minimum). The PWM switch turns off when the inductor current reaches this current threshold. The PWM switch remains off until the beginning of the next switching cycle. This protects the device and external components during an overload condition. When there is a sustained overcurrent condition more than 2 ms, the device shuts down and requires a POR or EN pin toggling to restart. The overcurrent shutdown protection can be disabled by E²PROM register through I²C interface. See ILIM (A5h) for E²PROM register table of ILIM shutdown protection programming.

7.3.10 Thermal Protection

When the junction temperature of the TPS61177A is over 150°C, the thermal protection circuit is triggered and shuts down the device immediately. The device automatically restarts when the junction temperature is back to less than 150°C with about 15°C hysteresis.

7.4.1 Mode Selection

The mixed-mode dimming method, analog dimming method, or direct PWM dimming method can be selected through the E²PROM register. See MODE (A0h) for E²PROM register table of dimming mode programming.

7.4.2 Analog and PWM Mixed Dimming Mode

In analog and PWM mixed mode, the TPS61177A features both analog dimming and PWM digital dimming. Analog dimming can provide potentially a lower power requirement for the same WLED brightness output because of a low voltage drop across each WLED when the current is low. Digital PWM dimming provides less WLED color distortion since the WLED current is held at 25% of full scale when the WLED is on.

The brightness control signal on the PWM pin is translated to a 10-bit digital signal and sent to control the six current regulators. Each current regulator outputs is DC, and PWM (25% < D_PWM < 100%) modulates the amplitude of the currents from 25% to 100% of preset full-scale current. For D_PWM < 25%, each CS turns on/off at translated duty cycle and same frequency to the input PWM, and in the WLED on duty current is regulated at 25% of full scale. Mixed-mode dimming provides the benefits of both the analog and PWM dimming. For 25% < D_PWM < 100%, analog dimming benefits the low power requirement and increases the power to brightness transform efficiency. At light load conditions, D_PWM < 25%, the PWM dimming provides both high accuracy brightness and low color distortion. Figure 19 provides the detailed timing diagram of the analog and PWM mixed dimming mode.

Figure 19. Analog and PWM Mixed-Mode Dimming Diagram

7.4.3 Analog Dimming Mode

In analog dimming mode, TPS61177A features pure analog dimming all over the brightness range of full-scale LED current. Analog dimming can provide potentially low power requirement for same WLED brightness output because of low voltage drop across each WLED when the current is low. In additional, the brightness control signal on the PWMB pin is translated to an up to 10-bits digital signal and sent to control the six current regulators. Each current regulator output DC modulates the amplitude of the currents from 1% to 100% of preset full-scale current. Figure 20 provides the detailed timing diagram of the analog dimming mode.

Figure 20. Analog-Mode Dimming Diagram

7.4.4 Direct PWM Dimming

In direct PWM mode, all current feedback channels are turned on and off and are synchronized with the input PWM signal. Figure 21 provides the detailed timing diagram of the direct PWM dimming mode.

Figure 21. Direct PWM-Mode Dimming Diagram

7.5.1 Configuration Parameters

Table 2 shows the memory map of the configuration parameters.

7.6.1 MODE (A0h)

The MODE register can be written to and read from.

7.6.2 CS (A1h)

The CS register can be written to and read from.

7.6.3 UVLO (A2h)

The UVLO register can be written to and read from.

7.6.4 FREQ (A3h)

The FREQ register can be written to and read from.

7.6.5 SR (A4h)

The SR register can be written to and read from.

7.6.6 ILIM (A5h)

The ILIM register can be written to and read from.

7.6.7 Control (FFh)

7.6.8 Example – Writing to a Single RAM Register

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of RAM register (A0h)
5. TPS61177A acknowledges
6. Bus master sends data to be written
7. TPS61177A acknowledges
8. Bus master sends STOP condition

Figure 29. Writing To A Single Ram Register

7.6.9 Example – Writing to Multiple RAM Registers

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h).
3. TPS61177A acknowledges
4. Bus master sends address of first RAM register to be written to (A0h)
5. TPS61177A acknowledges
6. Bus master sends data to be written to first RAM register
7. TPS61177A acknowledges
8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
9. TPS61177A acknowledges
10. Steps (8) and (9) repeated until data for final RAM register has been sent
11. TPS61177A acknowledges
12. Bus master sends STOP condition

Figure 30. Writing To Multiple Ram Registers

7.6.10 Example – Saving Contents of all RAM Registers to E²PROM

1. Pull high the Enable pin of TPS61177A
2. Pull the PWM pin of TPS61177A to low
3. Bus master sends START condition
4. Bus master sends 7-bit slave address plus low R/W bit (58h)
5. TPS61177A acknowledges
6. Bus master sends address of Control Register (FFh)
7. TPS61177A acknowledges
8. Bus master sends data to be written to the Control Register (80h)
9. TPS61177A acknowledges
10. Bus master sends STOP condition

Figure 31. Saving Contents Of All Ram Registers To E²PROM

The TPS61177A needs a 50-ms time period after receiving STOP condition for saving all RAM registers data to E²PROM. If bus master send 7-bit slave address to call TPS61177A again within 50-ms period, the TPS61177A pulls down the SCL line to LOW until the all RAM registers data saving to E²PROM is completed.

7.6.11 Example – Reading from a Single RAM Register

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends RAM register data
18. Bus master not acknowledges
19. Bus master sends STOP condition

Figure 32. Reading From A Single Ram Register

7.6.12 Example – Reading from a Single E²PROM Register

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends E²PROM register data
18. Bus master not acknowledges
19. Bus master sends STOP condition

Figure 33. Reading From A Single E²PROM Register

7.6.13 Example – Reading from Multiple RAM Registers

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of RAM register (A0h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends contents of first RAM register to be read
18. Bus master acknowledges
19. TPS61177A sends contents of second RAM register to be read
20. Bus master acknowledges
21. TPS61177A sends contents of third (last) RAM register to be read
22. Bus master not acknowledges
23. Bus master sends STOP condition

Figure 34. Reading From A Multiple Ram Register

7.6.14 Example – Reading from Multiple E²PROM Registers

1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (58h)
3. TPS61177A acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS61177A acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS61177A acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (58h)
11. TPS61177A acknowledges
12. Bus master sends address of E²PROM register (00h)
13. TPS61177A acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (59h)
16. TPS61177A acknowledges
17. TPS61177A sends contents of first E²PROM register to be read
18. Bus master acknowledges
19. TPS61177A sends contents of second E²PROM register to be read
20. Bus master acknowledges
21. TPS61177A sends contents of third (last) E²PROM register to be read
22. Bus master not acknowledges
23. Bus master sends STOP condition

Figure 35. Reading From Multiple E²PROM Registers