ZHCSIC0A September   2018  – November 2018 TPS61088-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用电路
  4. 4 修订历史记录
  5. 5 （说明 （续））
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable and Start-up
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Adjustable Switching Frequency
      4. 8.3.4 Adjustable Peak Current Limit
      5. 8.3.5 Overvoltage Protection
      6. 8.3.6 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
        1. 8.4.1.1 PWM Mode
        2. 8.4.1.2 PFM Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design with WEBENCH Tools
        2. 9.2.2.2 Setting Switching Frequency
        3. 9.2.2.3 Setting Peak Current Limit
        4. 9.2.2.4 Setting Output Voltage
        5. 9.2.2.5 Inductor Selection
        6. 9.2.2.6 Input Capacitor Selection
        7. 9.2.2.7 Output Capacitor Selection
        8. 9.2.2.8 Loop Stability
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 开发支持
        1. 12.1.2.1 使用 WEBENCH 工具创建定制设计
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.2.8 Loop Stability

The TPS61088-Q1 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network comprised of resister R5, ceramic capacitors C5 and C8 is connected to the COMP pin.

The power stage small signal loop response of constant off time (COT) with peak current control can be modeled by Equation 13.

Equation 13. TPS61088-Q1 eq_9_LVSCM8.gif

where

  • D is the switching duty cycle.
  • RO is the output load resistance.
  • Rsense is the equivalent internal current sense resistor, which is 0.08 Ω.
Equation 14. TPS61088-Q1 eq_9_where1_LVSCM8.gif

where

  • CO is output capacitor.
Equation 15. TPS61088-Q1 eq_9_where2_LVSCM8.gif

where

  • RESR is the equivalent series resistance of the output capacitor.
Equation 16. TPS61088-Q1 eq_9_where3_LVSCM8.gif

The COMP pin is the output of the internal transconductance amplifier. Equation 17 shows the small signal transfer function of compensation network.

Equation 17. TPS61088-Q1 eq_9_where4_LVSCW6.gif

where

  • GEA is the amplifier’s transconductance
  • REA is the amplifier’s output resistance
  • VREF is the refernce voltage at the FB pin
  • VOUT is the output voltage
  • ƒCOMP1, ƒCOMP2 are the poles' frequency of the compensation network.
  • ƒCOMZ is the zero's frequency of the compensation network.

The next step is to choose the loop crossover frequency, ƒC. The higher in frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.

Then set the value of R5, C5, and C8 (in Figure 13) by following these equations.

Equation 18. TPS61088-Q1 eq_10_LVSCW6.gif

where

  • ƒC is the selected crossover frequency.

The value of C5 can be set by Equation 19.

Equation 19. TPS61088-Q1 eq_11_LVSCM8.gif

The value of C8 can be set by Equation 20.

Equation 20. TPS61088-Q1 eq_12_LVSCM8.gif

If the calculated value of C8 is less than 10 pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output votlage ringing during the line and load transient.