ZHCSMV4A December   2020  – December 2022 TPS548B28

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO And Using External Bias On VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN For Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3™ Control Mode
      8. 7.3.8  Low-side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode™ Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a 3.3-V Bus
      5. 7.4.5 Powering the Device From a Split-rail Configuration
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Switching Frequency and the Operation Mode
        3. 8.2.2.3  Choose the Inductor
        4. 8.2.2.4  Set the Current Limit (TRIP)
        5. 8.2.2.5  Choose the Output Capacitor
        6. 8.2.2.6  Choose the Input Capacitors (CIN)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance On TI EVM
  9. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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Layout Guidelines

Before beginning a design using the device, consider the following:

  • Place the power components (including input and output capacitors, the inductor, and the IC) on the top side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid ground inner plane.
  • VIN decoupling capacitors are important for FET robustness. A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN pin 21 is required. The PGND vias for this decoupling capacitor must be placed so that the decoupling capacitor is closer to IC than the PGND vias. To lower ESL from via connection, two 8-mil vias are recommended for the PGND connection to inner PGND plane.
  • A 1-μF/25-V/X6S/0402 ceramic capacitor on VIN pin 10 is highly recommended. If this 0402 size capacitor is not used, the bigger size VIN decoupling capacitors (0603 or 0805 size) are required to be placed as close as possible to IC pin 10 and pin 11.
  • Two 1-μF/25-V/X6S/0402 ceramic capacitors on the bottom layer are recommended for high current applications (Iout > 13 A). One of these two capacitors must be centered between VIN pin 10 and pin 21. To have good connection for this capacitor, a VIN copper on bottom layer and two VIN vias are needed. The other one can be placed close to IC package just like a mirrored copy to the 0402 capacitor on top layer.
  • At least six PGND vias are required to be placed as close as possible to the PGND pins (pin 11 to pin 15). This minimizes parasitic impedance and also lowers thermal resistance.
  • Place the VCC decoupling capacitor (2.2-μF/6.3-V/X6S/0402 or 2.2-μF/6.3-V/X7R/0603) as close as possible to the device. Ensure the VCC decoupling loop is smallest.
  • Place BOOT capacitor as close as possible to the BOOT and SW pins. Use traces with a width of 12 mil or wider to route the connection. TI recommends using a 0.1-µF to 1-µF bootstrap capacitor with 10-V rating.
  • The PCB trace, which connects the SW pin and high-voltage side of the inductor, is defined as switch node. The switch node must be as short and wide as possible.
  • Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end sensing or remote sensing.
    • For remote sensing, the connections from the FB voltage divider resistors to the remote location must be a pair of PCB traces with at least 12-mil trace width, and must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be connected to VSNS– pin. The VOUT connection of the remote sensing signal must be connected to the feedback resistor divider with the lower feedback resistor terminated at VSNS– pin. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay away from any noise sources such as inductor and SW nodes, or high frequency clock lines. TI recommends to shield the pair of remote sensing lines with ground planes above and below.
    • For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of 0.1 μF or higher, and short VSNS– to AGND with shortest trace.
  • This device does not require a capacitor from SS/REFIN pin to AGND, thus TI does not recommend to place a capacitor from SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND capacitors exist, place CSS/REFIN-to-VSNS– more closely with shortest trace to VSNS– pin.
  • Pin 2 (AGND pin) must be connected to a solid PGND plane on inner layer. Use the common AGND via to connect the resistors to the inner ground plane if applicable.
  • See Section 8.4.2 for the layout recommendation.