ZHCSG55A November   2016  – February 2017 TPS54824

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-up into Pre-Biased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Soft-start Capacitor Selection
        7. 8.2.2.7  Undervoltage Lockout Set Point
        8. 8.2.2.8  Bootstrap Capacitor Selection
        9. 8.2.2.9  PGOOD Pull-up Resistor
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Alternate Layout Example
  11. 11器件和文档支持
    1. 11.1 接收文档更新通知
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

  • VIN and PGND traces should be as wide as possible to reduce trace impedance and improve heat dissipation.
  • An input capacitor is required on both VIN pins of the IC and must be placed as close as possible to the IC.
  • The PGND trace between the output capacitor and the PGND pin should be as wide as possible to minimize its trace impedance.
  • Provide sufficient vias for the input capacitor and output capacitor.
  • Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  • A separate VOUT path should be connected to the upper feedback resistor.
  • Voltage feedback loop should be placed away from the high-voltage switching trace. It is preferable to use ground copper near it as a shield.
  • The trace connected to the FB node should be as small as possible to avoid noise coupling.
  • Place components connected to the RT/CLK, FB, COMP and SS/TRK pins as close to the IC as possible and minimize traces connected to these pins to avoid noise coupling.
  • AGND must be connected to PGND on the PCB. Connect AGND to PGND in a region away from switching currents.

Layout Example

Figure 51 through Figure 54 shows an example PCB layout and the following list provides a description of each layer.

  • The top layer has all components and the main traces for VIN, SW, VOUT and PGND. Both VIN pins are bypassed with two input capacitors placed as close as possible to the IC. Multiple vias are placed near the input and output capacitors. The AGND trace is connected to PGND with a wide trace away from the input capacitors to minimize switching noise.
  • Midlayer 1 is used to route the BOOT pin to the BOOT-SW capacitor (CBT). The rest of this layer is covered with PGND.
  • Midlayer 2 has a wide trace connecting both VIN pins of the IC. It also has a parallel trace for VOUT to minimize trace resistance. The rest of this layer is covered with PGND.
  • The bottom layer has the trace connecting the FB resistor divider to VOUT at the point of regulation. PGND is filled into the rest of this layer to aid with thermal performance.
TPS54824 Layout_top_slvsdc9.gif Figure 51. TPS54824 Layout Top
TPS54824 Layout_mid2_slvsdc9.gif Figure 53. TPS54824 Layout Midlayer 2
TPS54824 Layout_mid1_slvsdc9.gif Figure 52. TPS54824 Layout Midlayer 1
TPS54824 Layout_bot_slvsdc9.gif Figure 54. TPS54824 Layout Bottom

Alternate Layout Example

Figure 55 through Figure 58 shows an alternate example PCB layout with unsymmetrical placement of the input capacitors and output capacitors. Both VIN pins are still bypassed with an input capacitor placed as close as possible to the IC.

TPS54824 Layout_alternate_top_slvsdc9.gif Figure 55. TPS54824 Alternate Layout Top
TPS54824 Layout_alternate_mid2_slvsdc9.gif Figure 57. TPS54824 Alternate Layout Midlayer 2
TPS54824 Layout_alternate_mid1_slvsdc9.gif Figure 56. TPS54824 Alternate Layout Midlayer 1
TPS54824 Layout_alternate_bot_slvsdc9.gif Figure 58. TPS54824 Alternate Layout Bottom