ZHCS338D October   2011  – August 2016 TPS54295

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Auto-Skip Eco-Mode Control
      4. 7.3.4 Soft Start and Prebiased Soft Start
      5. 7.3.5 Overcurrent Protection
      6. 7.3.6 Overvoltage and Undervoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Eco-Mode Operation
      3. 7.4.3 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Resistors Selection
        2. 8.2.2.2 Output Filter Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Bootstrap Capacitor Selection
        5. 8.2.2.5 VREG5 Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档　
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View
RSA Package
16-Pin VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME HTSSOP VQFN
EN1 5 7 I Enable. Pull high to enable the corresponding (1 or 2) converter.
EN2 12 14
GND 8 10 I/O Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.
PGND1 4 6 I/O Ground returns for low-side MOSFETs. Input of current comparator.
PGND2 13 15
SS1 6 8 O Soft-start programming pin. Connect capacitor from SSx pin to GND to program soft-start time.
SS2 11 13
SW1 3 5 I/O Switch node connections for both the high-side NFETs and low-side NFETs. Input of current comparator.
SW2 14 16
VBST1 2 14 I Supply input for high-side NFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx.
VBST2 15 1
VFB1 7 9 I D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
VFB2 10 12
VIN1 1 3 I Power inputs and connects to both high-side NFET drains. Supply Input for 5.5-V linear regulator.
VIN2 16 2
VREG5 9 11 O Output of 5.5-V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least 1 µF. VREG5 is active when VIN1 is added.
Thermal Pad — — — Thermal pad of the package. Must be soldered to ground to achieve appropriate dissipation. Must be connected to GND.